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* [CodeGenPrep] Skip merging empty case blocksJun Bum Lim2016-12-161-1/+1
| | | | | | | | | | | | | | This is recommit of r287553 after fixing the invalid loop info after eliminating an empty block and unit test failures in AVR and WebAssembly : Summary: Merging an empty case block into the header block of switch could cause ISel to add COPY instructions in the header of switch, instead of the case block, if the case block is used as an incoming block of a PHI. This could potentially increase dynamic instructions, especially when the switch is in a loop. I added a test case which was reduced from the benchmark I was targetting. Reviewers: t.p.northover, mcrosier, manmanren, wmi, joerg, davidxl Subscribers: joerg, qcolombet, danielcdh, hfinkel, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22696 llvm-svn: 289988
* [AVR] Add a test for 64-bit left shiftsDylan McKay2016-12-161-0/+8
| | | | llvm-svn: 289936
* [AVR] Support floats in the instrumention passDylan McKay2016-12-151-4/+21
| | | | | | This also refactors some common code into the 'GetTypeName' method. llvm-svn: 289803
* [AVR] Add a function instrumentation passDylan McKay2016-12-141-0/+45
| | | | | | This will be used for an on-chip test suite. llvm-svn: 289641
* [AVR] Add an 'relax memory operation' passDylan McKay2016-12-131-0/+31
| | | | | | | | | | | | | | | | | | | | | | Summary: This pass will be used to relax instructions which use out of bounds memory accesses to equivalent operations that can work with the addresses. The pass currently implements relaxation for the STDWPtrQRr instruction. Without this pass, an assertion error would be hit in the pseudo expansion pass. In the future, we will need to add more instructions to this pass. We can do that on a case-by-case basic. Reviewers: arsenm, kparzysz Subscribers: wdng, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D27650 llvm-svn: 289517
* [AVR] Add calling convention CodeGen testsDylan McKay2016-12-113-0/+167
| | | | | | This adds CodeGen tests for the AVR C calling convention. llvm-svn: 289369
* [AVR] Add a test to validate a simple 'blinking led' programDylan McKay2016-12-111-0/+125
| | | | llvm-svn: 289362
* [AVR] Fix and clean up the inline assembly testsDylan McKay2016-12-104-337/+338
| | | | | | | | | | There was a bug where we would hit an assertion if 'Q' was used as a constraint. I also removed hardcoded register names to prefer regexes so the tests don't break when the register allocator changes. llvm-svn: 289325
* [AVR] Explicitly set the target in all CodeGen testsDylan McKay2016-12-104-4/+4
| | | | | | This seems to have caused failures on the buildbot. llvm-svn: 289324
* [AVR] Use the register scavenger when expanding 'LDDW' instructionsDylan McKay2016-12-101-12/+13
| | | | | | | | | | | | Summary: This gets rid of the hardcoded 'r0' that was used previously. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27567 llvm-svn: 289322
* [AVR] Support stores to undefined pointersDylan McKay2016-12-101-0/+13
| | | | | | This would previously trigger an assertion error in AVRISelDAGToDAG. llvm-svn: 289321
* [AVR] Remove a set of redundant testsDylan McKay2016-12-094-88/+0
| | | | | | This fixes the build. llvm-svn: 289201
* [AVR] Add tests for a large number of pseudo instructionsDylan McKay2016-12-0927-4/+560
| | | | | | This adds MIR tests for 24 pseudo instructions. llvm-svn: 289191
* [AVR] Add MIR tests for pseudo instruction expansionsDylan McKay2016-12-0813-0/+308
| | | | | | This adds tests for 13 pseudo instruction expansions. llvm-svn: 289039
* [AVR] Add MIR tests for a few pseudo instructionsDylan McKay2016-12-083-0/+72
| | | | llvm-svn: 289031
* [AVR] Expand 'SELECT_CC' nodes whereever possibleDylan McKay2016-12-071-2/+0
| | | | llvm-svn: 288905
* [AVR] Move a pseudo expansion test into a folderDylan McKay2016-12-071-0/+0
| | | | llvm-svn: 288899
* [AVR] Allow loading from stack slots where src and dest registers are identicalDylan McKay2016-12-072-56/+33
| | | | | | Fixes PR 31256 llvm-svn: 288897
* [AVR] Remove 'XFAIL' from a CodeGen testDylan McKay2016-12-041-1/+0
| | | | | | This seems to be fixed as of r288052. llvm-svn: 288618
* Un-XFAIL an AVR CodeGen testDylan McKay2016-11-261-1/+0
| | | | llvm-svn: 287958
* [AVR] Mark the 'select-must-add-unconditional-jump' test as 'XFAIL'Dylan McKay2016-11-241-0/+1
| | | | llvm-svn: 287871
* [AVR] Remove some accidentally-commited code that broke the botsDylan McKay2016-11-171-24/+0
| | | | | | | | | This is a remnant of an on-chip unit testing tool that has since been moved out-of-tree. It was accidentally committed in r287162. llvm-svn: 287180
* [AVR] Fix basic block naming in ctlz and cttz testsDylan McKay2016-11-162-4/+4
| | | | | | The branch selector would change the names. llvm-svn: 287174
* [AVR] Add tests for counting leading/trailing zerosDylan McKay2016-11-162-0/+88
| | | | | | This adds two test files that verify the 'cttz' and 'ctlz' operations. llvm-svn: 287172
* [AVR] Add the pseudo instruction expansion passDylan McKay2016-11-1633-0/+2979
| | | | | | | | | | | | | | | | | | Summary: A lot of the pseudo instructions are required because LLVM assumes that all integers of the same size as the pointer size are legal. This means that it will not currently expand 16-bit instructions to their 8-bit variants because it thinks 16-bit types are legal for the operations. This also adds all of the CodeGen tests that required the pass to run. Reviewers: arsenm, kparzysz Subscribers: wdng, mgorny, modocache, llvm-commits Differential Revision: https://reviews.llvm.org/D26577 llvm-svn: 287162
* [AVR] Add a selection of CodeGen testsDylan McKay2016-11-0919-0/+556
| | | | | | | | | | | | Summary: This adds all of the CodeGen tests which currently pass. Reviewers: arsenm, kparzysz Subscribers: japaric, wdng Differential Revision: https://reviews.llvm.org/D26388 llvm-svn: 286418
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-10-111-0/+78
| | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, when allocating unspillable live ranges, we would never attempt to split. We would always bail out and try last ditch graph recoloring. This patch changes this by attempting to split all live intervals before performing recoloring. This fixes LLVM bug PR14879. I can't add test cases for any backends other than AVR because none of them have small enough register classes to trigger the bug. Reviewers: qcolombet Subscribers: MatzeB Differential Revision: https://reviews.llvm.org/D25070 llvm-svn: 283838
* Requires the AVR backend for running test/CodeGen/AVRMehdi Amini2016-10-081-0/+3
| | | | llvm-svn: 283653
* Allow a maximum of 64 bits to be returned in registersDylan McKay2016-10-081-0/+9
| | | | | | | | The rest spills to the stack Authored by Jake Goulding llvm-svn: 283635
* [AVR] Expand MULHS for all typesDylan McKay2016-10-082-0/+53
| | | | | | | | | | Once MULHS was expanded, this exposed an issue where the condition register was thought to be 16-bit. This caused an attempt to copy a 16-bit register to an 8-bit register. Authored by Jake Goulding llvm-svn: 283634
* Revert "[RegAllocGreedy] Attempt to split unspillable live intervals"Dylan McKay2016-09-301-78/+0
| | | | | | It was accidentally committed. llvm-svn: 282855
* [RegAllocGreedy] Attempt to split unspillable live intervalsDylan McKay2016-09-301-0/+78
Summary: Previously, when allocating unspillable live ranges, we would never attempt to split. We would always bail out and try last ditch graph recoloring. This patch changes this by attempting to split all live intervals before performing recoloring. This fixes LLVM bug PR14879. I can't add test cases for any backends other than AVR because none of them have small enough register classes to trigger the bug. Reviewers: qcolombet Subscribers: MatzeB Differential Revision: https://reviews.llvm.org/D25070 llvm-svn: 282852
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