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* Materialize global addresses via movt/movw pair, this is always betterAnton Korobeynikov2009-11-241-0/+20
| | | | | | | | | | | | | than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). llvm-svn: 89720
* move fconst[sd] to UAL. <rdar://7414913>Jim Grosbach2009-11-232-5/+5
| | | | llvm-svn: 89700
* Convert ARM tests to FileCheck for PR5307.Edward O'Callaghan2009-11-227-35/+137
| | | | llvm-svn: 89593
* Forgot to alter RUN line when converting to FileCheck.Edward O'Callaghan2009-11-221-1/+1
| | | | llvm-svn: 89588
* Fix for bad FileCheck converts in revision 89584.Edward O'Callaghan2009-11-221-3/+2
| | | | llvm-svn: 89586
* Convert a few tests to FileCheck for PR5307.Edward O'Callaghan2009-11-224-6/+18
| | | | llvm-svn: 89584
* Revert 89562. We're being sneakier than I was giving us credit for, and thisJim Grosbach2009-11-213-4/+2
| | | | | | isn't necessary. llvm-svn: 89568
* Darwin requires a frame pointer for all non-leaf functions to support correctJim Grosbach2009-11-213-2/+4
| | | | | | backtraces. llvm-svn: 89562
* Remat VLDRD from constpool. Clean up some instruction property specifications.Evan Cheng2009-11-201-0/+65
| | | | llvm-svn: 89478
* Fix codegen of conditional move of immediates. We were not making use of the ↵Evan Cheng2009-11-202-1/+49
| | | | | | immediate forms of cmov instructions at all. llvm-svn: 89423
* Fix buildbots.Bob Wilson2009-11-181-1/+1
| | | | llvm-svn: 89274
* Tail duplication still needs to iterate. Duplicating new instructions ontoBob Wilson2009-11-181-0/+64
| | | | | | the tail of a block may make that block a new candidate for duplication. llvm-svn: 89264
* Forgot to commit test fixesAnton Korobeynikov2009-11-171-2/+2
| | | | llvm-svn: 89138
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-2/+3
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* - Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.Evan Cheng2009-11-141-1/+2
| | | | | | | | - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. llvm-svn: 88745
* Add radar number.Evan Cheng2009-11-141-0/+1
| | | | llvm-svn: 88739
* Fix PR5412: Fix an inverted check and another missing sub-register check.Evan Cheng2009-11-142-0/+235
| | | | llvm-svn: 88738
* Fix PR5411. Bug in UpdateKills. A reg def partially define its super-registers.Evan Cheng2009-11-131-0/+42
| | | | llvm-svn: 88719
* Fix PR5410: LiveVariables lost subreg def:Evan Cheng2009-11-131-0/+20
| | | | | | | | | | | | | | D0<def,dead> = ... ... = S0<use, kill> S0<def> = ... ... D0<def> = The first D0 def is correctly marked dead, however, livevariables should have added an implicit def of S0 or we end up with a use without a def. llvm-svn: 88690
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-0935-116/+119
| | | | llvm-svn: 86494
* It turns out that the testcase in question uncovered subreg-handling bug.Anton Korobeynikov2009-11-071-0/+1
| | | | | | | Add assert in asmprinter to catch such cases and xfail the tests. PR is to be filled. llvm-svn: 86375
* Honour subreg machine operands during asmprintingAnton Korobeynikov2009-11-061-0/+64
| | | | llvm-svn: 86303
* Print VMOV (immediate) operands as hexadecimal values. Apple's assemblerBob Wilson2009-11-061-0/+20
| | | | | | | | | will not accept negative values for these. LLVM's default operand printing sign extends values, so that valid unsigned values appear as negative immediates. Print all VMOV immediate operands as hex values to resolve this. Radar 7372576. llvm-svn: 86301
* Remove ARMPCLabelIndex from ARMISelLowering. Use ↵Evan Cheng2009-11-061-4/+4
| | | | | | ARMFunctionInfo::createConstPoolEntryUId() instead. llvm-svn: 86294
* Update these tests for the new label names.Dan Gohman2009-11-051-3/+3
| | | | llvm-svn: 86192
* Attempt again to fix buildbot failures: make expected output less specificBob Wilson2009-11-051-12/+9
| | | | | | and compile with -mtriple to specify *-apple-darwin targets. llvm-svn: 86081
* Fix broken test.Bob Wilson2009-11-041-2/+2
| | | | llvm-svn: 86045
* Add test for ARM indirectbr codegen.Bob Wilson2009-11-041-0/+63
| | | | llvm-svn: 86042
* fconsts / fconstd immediate should be proceeded with #.Evan Cheng2009-11-031-4/+4
| | | | llvm-svn: 85952
* Re-apply 85799. It turns out my code isn't buggy.Evan Cheng2009-11-031-1/+1
| | | | llvm-svn: 85947
* Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.Evan Cheng2009-11-032-1/+64
| | | | llvm-svn: 85871
* Revert r85049, it is causing PR5367Anton Korobeynikov2009-11-031-1/+1
| | | | llvm-svn: 85847
* Revert 85799 for now. It might be breaking llvm-gcc driver.Evan Cheng2009-11-021-1/+1
| | | | llvm-svn: 85827
* Initilize the machine LICM CSE map upon the first time an instruction is ↵Evan Cheng2009-11-021-1/+1
| | | | | | | | | | hoisted to the loop preheader. Add instructions which are already in the preheader block that may be common expressions of those that are hoisted out. These does get a few more instructions CSE'ed. llvm-svn: 85799
* Remove an irrelevant and poorly reduced test case.Evan Cheng2009-11-021-414/+0
| | | | llvm-svn: 85794
* Handle splats of undefs properly. This includes the testcase for PR5364 as well.Anton Korobeynikov2009-11-021-0/+20
| | | | llvm-svn: 85767
* 64-bit FP loads & stores operate on both NEON and VFP pipelines.Anton Korobeynikov2009-11-021-0/+37
| | | | llvm-svn: 85765
* vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid usingJim Grosbach2009-10-312-3/+5
| | | | | | them for scalar floating point operations for now. llvm-svn: 85697
* Update test to be more explicit about what instruction sequences are ↵Jim Grosbach2009-10-311-3/+16
| | | | | | expected for each operation. llvm-svn: 85689
* Expand 64-bit logical shift right inlineJim Grosbach2009-10-311-1/+1
| | | | llvm-svn: 85687
* Expand 64-bit arithmetic shift right inlineJim Grosbach2009-10-311-1/+1
| | | | llvm-svn: 85685
* Expand 64 bit left shift inline rather than using the libcall. For now, thisJim Grosbach2009-10-311-1/+1
| | | | | | | is unconditional. Making it still use the libcall when optimizing for size would be a good adjustment. llvm-svn: 85675
* Add missing colons for FileCheck.Benjamin Kramer2009-10-311-1/+1
| | | | llvm-svn: 85674
* Convert to FileCheckJim Grosbach2009-10-311-5/+9
| | | | llvm-svn: 85673
* This fixes functions likeRafael Espindola2009-10-301-0/+17
| | | | | | | | | | | void f (int a1, int a2, int a3, int a4, int a5,...) In ARMTargetLowering::LowerFormalArguments if the function has 4 or more regular arguments we used to set VarArgsFrameIndex using an offset of 0, which is only correct if the function has exactly 4 regular arguments. llvm-svn: 85590
* Use fconsts and fconstd to materialize small fp constants.Evan Cheng2009-10-281-0/+33
| | | | llvm-svn: 85362
* Add missing testcase.Rafael Espindola2009-10-271-0/+14
| | | | llvm-svn: 85266
* Fix the rest of the ARM failures by converting them to FileCheck.Bob Wilson2009-10-277-39/+74
| | | | llvm-svn: 85208
* Fix some more failures by converting to FileCheck.Bob Wilson2009-10-277-23/+44
| | | | llvm-svn: 85207
* Convert to FileCheck, fixing failure due to tab change in the process.Bob Wilson2009-10-271-4/+3
| | | | llvm-svn: 85204
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