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* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-272-0/+54
| | | | | | | | These instructions aren't particularly complicated and it's well worth having patterns for some reasonably useful LLVM IR that will match them. Soon we should be able to switch Clang over to producing this natural version. llvm-svn: 189335
* Debug Info: add an identifier field to DICompositeType.Manman Ren2013-08-2612-42/+42
| | | | | | | | | | | | | | | | | | DICompositeType will have an identifier field at position 14. For now, the field is set to null in DIBuilder. For DICompositeTypes where the template argument field (the 13th field) was optional, modify DIBuilder to make sure the template argument field is set. Now DICompositeType has 15 fields. Update DIBuilder to use NULL instead of "i32 0" for null value of a MDNode. Update verifier to check that DICompositeType has 15 fields and the last field is null or a MDString. Update testing cases to include an extra field for DICompositeType. The identifier field will be used by type uniquing so a front end can genearte a DICompositeType with a unique identifer. llvm-svn: 189282
* ARM: Enable machine verifier for a few more tests.Jim Grosbach2013-08-262-3/+3
| | | | | | | | | Now that fast-isel is in better shape, we can enable the machine verifier for these tests, too. rdar://12594152 llvm-svn: 189275
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 llvm-svn: 189274
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-1/+1
| | | | | | | | | Constant pool and global value reference instructions need more restricted register classes than plain GPR. rdar://12594152 llvm-svn: 189270
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-3/+3
| | | | llvm-svn: 189109
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-231-0/+46
| | | | llvm-svn: 189103
* [stack protector] Work around an issue with the BMOVPCB_CALL instruction on ↵Michael Gottesman2013-08-221-0/+32
| | | | | | | | | | ARM by disabling does not return on __stack_chk_fail. This is to fix the bots while I look to see if there is something I can do here. rdar://14811848 llvm-svn: 189076
* Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to ↵Bill Wendling2013-08-221-2/+2
| | | | | | 'false'. llvm-svn: 189068
* Fix some tests. The 'false' version just omits the attribute altogether.Bill Wendling2013-08-221-1/+1
| | | | llvm-svn: 189065
* [Debug Info Tests] Update testing cases.Manman Ren2013-08-221-2/+1
| | | | | | | | | A single metadata will not span multiple lines. This also helps me with my script to automatic update the testing cases. A debug info testing case should have a llvm.dbg.cu. Do not use hard-coded id for debug nodes. llvm-svn: 189033
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-221-0/+309
| | | | | | | | This uses the ARMcmov pattern that Tim cleaned up in r188995. Thanks to Simon Tatham for his floating point help! llvm-svn: 189024
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-222-2/+2
| | | | | | we pass these tests with -verify-machineinstrs. llvm-svn: 189006
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-0/+23
| | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. llvm-svn: 189002
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-223-7/+7
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* ARM: respect tied 64-bit inlineasm operands when printingTim Northover2013-08-221-0/+10
| | | | | | | The code for 'Q' and 'R' operand modifiers needs to look through tied operands to discover the register class. llvm-svn: 188990
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-08-213-39/+24
| | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 188944
* ARM: Fix fast-isel copy/paste-o.Jim Grosbach2013-08-201-5/+6
| | | | | | | | | | | | Update testcase to be more careful about checking register values. While regexes are general goodness for these sorts of testcases, in this example, the registers are constrained by the calling convention, so we can and should check their explicit values. rdar://14779513 llvm-svn: 188819
* ARM: implement some simple f64 materializations.Tim Northover2013-08-202-3/+70
| | | | | | | | Previously we used a const-pool load for virtually all 64-bit floating values. Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov" instructions of one stripe or another. llvm-svn: 188773
* ARM: make sure we keep inline asm operands tied.Tim Northover2013-08-181-0/+9
| | | | | | | | When patching inlineasm nodes to use GPRPair for 64-bit values, we were dropping the information that two operands were tied, which effectively broke the live-interval of vregs affected. llvm-svn: 188643
* ARM: Properly constrain comparison fastisel register classes.Jim Grosbach2013-08-161-1/+1
| | | | | | | | Ongoing 'make the verifier happy' improvements to ARM fast-isel. rdar://12594152 llvm-svn: 188595
* ARM: Fast-isel register class constrain for extends.Jim Grosbach2013-08-166-17/+17
| | | | | | | | | | Properly constrain the operand register class for instructions used in [sz]ext expansion. Update more tests to use the verifier now that we're getting the register classes correct. rdar://12594152 llvm-svn: 188594
* ARM: Fix more fast-isel verifier failures.Jim Grosbach2013-08-161-1/+1
| | | | | | | | | | | | | Teach the generic instruction selection helper functions to constrain the register classes of their input operands. For non-physical register references, the generic code needs to be careful not to mess that up when replacing references to result registers. As the comment indicates for MachineRegisterInfo::replaceRegWith(), it's important to call constrainRegClass() first. rdar://12594152 llvm-svn: 188593
* ARM: Clean up fast-isel machine verifier errors.Jim Grosbach2013-08-169-41/+41
| | | | | | | | | | | | | Lots of machine verifier errors result from using a plain GPR regclass for incoming argument copies. A more restrictive rGPR class is more appropriate since it more accurately represents what's happening, plus it lines up better with isel later on so the verifier is happier. Reduces the number of ARM fast-isel tests not running with the verifier enabled by over half. rdar://12594152 llvm-svn: 188592
* When initializing the PIC global base register on ARM/ELF add pc to fix the ↵Benjamin Kramer2013-08-161-0/+4
| | | | | | | | | | address. This unbreaks PIC with fast isel on ELF targets (PR16717). The output matches what GCC and SDag do for PIC but may not cover all of the many flavors of PIC that exist. llvm-svn: 188551
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. llvm-svn: 188513
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-0/+64
| | | | | | | | | | | | | | When determining if two different loads are from the same base address, this patch allows one load to use a t2LDRi8 address mode and another to use a t2LDRi12 address mode. The current implementation is very conservative and this allows the case of differing Thumb2 byte loads to be considered. Allowing these differing modes instead of forcing the exact same opcode is useful for situations where one opcodes loads from a base address+1 and a second opcode loads for a base address-1. Patch by Daniel Stewart. llvm-svn: 188385
* DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)Jim Grosbach2013-08-131-0/+14
| | | | | | | | | | | | | | | | | | | | | | | A common idiom is to use zero and all-ones as sentinal values and to check for both in a single conditional ("x != 0 && x != (unsigned)-1"). That generates code, for i32, like: testl %edi, %edi setne %al cmpl $-1, %edi setne %cl andb %al, %cl With this transform, we generate the simpler: incl %edi cmpl $1, %edi seta %al Similar improvements for other integer sizes and on other platforms. In general, combining the two setcc instructions into one is better. rdar://14689217 llvm-svn: 188315
* Fix FileCheck --check-prefix lines.Tim Northover2013-08-124-22/+22
| | | | | | | | | | Various tests had sprung up over the years which had --check-prefix=ABC on the RUN line, but "CHECK-ABC:" later on. This happened to work before, but was strictly incorrect. FileCheck is getting stricter soon though. Patch by Ron Ofir. llvm-svn: 188173
* Make sure that if we're going to attempt to add a type to a DIE thatEric Christopher2013-08-081-5/+5
| | | | | | | | | | | | the type exists. Fix up cases where we weren't checking for optional types and add an assert to addType to make sure we catch this in the future. Fix up a testcase that was using the tag for DW_TAG_array_type when it meant DW_TAG_enumeration_type. llvm-svn: 187963
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-061-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Also remove checking of llvm.dbg.sp since it is not used in generating dwarf. Current state of Finder: DebugInfoFinder tries to list all debug info MDNodes used in a module. To list debug info MDNodes used by an instruction, DebugInfoFinder provides processDeclare, processValue and processLocation to handle DbgDeclareInst, DbgValueInst and DbgLoc attached to instructions. processModule will go through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes used by the CUs. TODO: 1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We need to add a list of variables that are used by DbgDeclareInst and DbgValueInst. 2> MDString fields should be null or isa<MDString> and MDNode fields should be null or isa<MDNode>. We currently use empty string or int 0 to represent null. 3> Go though Verify functions and make sure that they check field types. 4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each testing case has a llvm.dbg.cu. Re-apply r187609 with fix to pass ocaml binding. vmcore.ml generates a debug location with scope being metadata !{}, in verifier we treat this as a null scope. llvm-svn: 187812
* ARM: implement allowTruncateForTailCallTim Northover2013-08-061-0/+111
| | | | | | | Now that it's in place, it seems silly not to let ARM make use of the extra tail call opportunities. llvm-svn: 187795
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-021-4/+3
| | | | | | | | instructions." in an attempt to bring back some bots. This reverts commit r187609. llvm-svn: 187638
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-011-20/+30
| | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. llvm-svn: 187618
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-011-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | Also remove checking of llvm.dbg.sp since it is not used in generating dwarf. Current state of Finder: DebugInfoFinder tries to list all debug info MDNodes used in a module. To list debug info MDNodes used by an instruction, DebugInfoFinder provides processDeclare, processValue and processLocation to handle DbgDeclareInst, DbgValueInst and DbgLoc attached to instructions. processModule will go through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes used by the CUs. TODO: 1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We need to add a list of variables that are used by DbgDeclareInst and DbgValueInst. 2> MDString fields should be null or isa<MDString> and MDNode fields should be null or isa<MDNode>. We currently use empty string or int 0 to represent null. 3> Go though Verify functions and make sure that they check field types. 4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each testing case has a llvm.dbg.cu. llvm-svn: 187609
* This test may have been sensitive to the ARM ABI...Andrew Trick2013-07-301-1/+1
| | | | llvm-svn: 187442
* MI Sched fix: assert "Disconnected LRG within the scheduling region."Andrew Trick2013-07-301-1/+54
| | | | llvm-svn: 187435
* [ARM] check bitwidth in PerformORCombineSaleem Abdulrasool2013-07-301-0/+32
| | | | | | | | | | | | | When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> llvm-svn: 187404
* [DAGCombiner] insert_vector_elt: Avoid building a vector twice.Quentin Colombet2013-07-301-0/+26
| | | | | | | | | | | | | | | | This patch prevents the following combine when the input vector is used more than once. insert_vector_elt (build_vector elt0, ..., eltN), NewEltIdx, idx => build_vector elt0, ..., NewEltIdx, ..., eltN The reasons are: - Building a vector may be expensive, so try to reuse the existing part of a vector instead of creating a new one (think big vectors). - elt0 to eltN now have two users instead of one. This may prevent some other optimizations. llvm-svn: 187396
* Debug Info: enable verifier for testing cases.Manman Ren2013-07-293-3/+3
| | | | llvm-svn: 187375
* Debug Info: update testing cases to pass verifier.Manman Ren2013-07-291-4/+4
| | | | llvm-svn: 187362
* Allow generation of vmla.f32 instructions when targeting Cortex-A15. The ↵Silviu Baranga2013-07-291-1/+25
| | | | | | patch also adds the VFP4 feature to Cortex-A15 and fixes the DontUseFusedMAC predicate so that we can still generate vmla.f32 instructions on non-darwin targets with VFP4. llvm-svn: 187349
* Debug Info Verifier: verify SPs in llvm.dbg.sp.Manman Ren2013-07-277-41/+45
| | | | | | | | Also always add DIType, DISubprogram and DIGlobalVariable to the list in DebugInfoFinder without checking them, so we can verify them later on. llvm-svn: 187285
* Debug Info Verifier: enable verification of DICompileUnit.Manman Ren2013-07-264-4/+9
| | | | | | | | We used to call Verify before adding DICompileUnit to the list, and now we remove the check and always add DICompileUnit to the list in DebugInfoFinder, so we can verify them later on. llvm-svn: 187237
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-253-12/+13
| | | | | | | Make sure the context field of DIType is MDNode. Fix testing cases to make them pass the verifier. llvm-svn: 187150
* Evict local live ranges if they can be reassigned.Andrew Trick2013-07-251-4/+2
| | | | | | | | | | | | | | | | The previous change to local live range allocation also suppressed eviction of local ranges. In rare cases, this could result in more expensive register choices. This commit actually revives a feature that I added long ago: check if live ranges can be reassigned before eviction. But now it only happens in rare cases of evicting a local live range because another local live range wants a cheaper register. The benefit is improved code size for some benchmarks on x86 and armv7. I measured no significant compile time increase and performance changes are noise. llvm-svn: 187140
* Allocate local registers in order for optimal coloring.Andrew Trick2013-07-256-36/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
* Current batch of -disable-debug-info-verifier.Rafael Espindola2013-07-254-4/+4
| | | | llvm-svn: 187130
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-254-45/+45
| | | | | | | | Make sure the context and type fields are MDNodes. We will generate verification errors if those fields are non-empty strings. Fix testing cases to make them pass the verifier. llvm-svn: 187106
* Update testing cases to pass debug info verifier.Manman Ren2013-07-241-13/+13
| | | | llvm-svn: 187083
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