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* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-308-37/+37
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [ARM][DAG] Revert Disable post-legalization store merge for ARMNirav Dave2017-11-291-31/+19
| | | | | | | | Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331
* [ARM GlobalISel] Fix selecting G_BRCONDDiana Picus2017-11-292-2/+2
| | | | | | | | | | | | | When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
* [ARM] Add support for armv7e-m to the .arch directiveOliver Stannard2017-11-291-0/+3
| | | | | | | | | | | This will allow compilation of assembly files targeting armv7e-m without having to specify the Tag_CPU_arch attribute as a workaround. Differential revision: https://reviews.llvm.org/D40370 Patch by Ian Tessier! llvm-svn: 319303
* [globalisel][tablegen] Fix PR35375 by sign-extending the table value to ↵Daniel Sanders2017-11-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | match getConstantVRegVal() Summary: From the bug report: > The problem is that it fails when trying to compare -65536 (or 4294901760) to 0xFFFF,0000. This is because the > constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non > extended 64 bit version expected by TableGen. > > In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not > sign extend. This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check. Thanks to Diana Picus for the detailed bug report. Reviewers: rovka Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40532 llvm-svn: 319252
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-285-9/+9
| | | | | | | | | | | As part of the unification of the debug format and the MIR format, always print registers as lowercase. * Only debug printing is affected. It now follows MIR. Differential Revision: https://reviews.llvm.org/D40417 llvm-svn: 319187
* [DAGCombine] Disable finding better chains for stores at O0Simon Dardis2017-11-281-24/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unoptimized IR can have linear sequences of stores to an array, where the initial GEP for the first store is formed from the pointer to the array, and the GEP for each store after the first is formed from the previous GEP with some offset in an inductive fashion. The (large) resulting DAG when analyzed by DAGCombine undergoes an excessive number of combines as each store node is examined every time its' offset node is combined with any child of the offset. One of the transformations is findBetterNeighborChains which assists MergeConsecutiveStores. The former relies on repeated chain walking to do its' work, however MergeConsecutiveStores is disabled at O0 which makes the transformation redundant. Any optimization level other than O0 would invoke InstCombine which would resolve the chain of GEPs into flat base + offset GEP for each store which does not exhibit the repeated examination of each store to the array. Disabling this optimization fixes an excessive compile time issue (30~ minutes for the test case provided) at O0. Reviewers: niravd, craig.topper, t.p.northover Differential Revision: https://reviews.llvm.org/D40193 llvm-svn: 319142
* ARM: Fix PR32578Matthias Braun2017-11-281-0/+27
| | | | | | | | | | https://llvm.org/PR32578 I simplified and converted the reproducer into a lit test. Patch by Vedant Kumar! llvm-svn: 319130
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-271-19/+31
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov2017-11-272-5/+5
| | | | | | | | | | | | | | The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from. The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4). Differential revision: https://reviews.llvm.org/D40305 llvm-svn: 319014
* [ARM GlobalISel] Support G_FDIV for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | | TableGen already generates code for selecting a G_FDIV, so we only need to add a test. For the legalizer and reg bank select, we do the same thing as for the other floating point binary operations: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318915
* [ARM GlobalISel] Support G_FMUL for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910
* [MI scheduler] Fix VADD and VSUB in cortex-a57 modelEugene Leviant2017-11-212-0/+52
| | | | | | | | This patch fixes instregex for interger vector add/sub instructions Differential revision: https://reviews.llvm.org/D40254 llvm-svn: 318749
* [ARM GlobalISel] Add comment for r318398. NFC.Diana Picus2017-11-211-0/+5
| | | | | | | Mention the purpose of the BICri tests added by r318398, as requested in post-commit review. llvm-svn: 318747
* [ARM GlobalISel] Add test for RSBri. NFCDiana Picus2017-11-201-0/+58
| | | | | | | | Add instruction selector test for RSBri, which is derived from AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is derived from the very similar AsI1_bin_irs pattern. llvm-svn: 318643
* [ARM GlobalISel] Clean up binary operator tests. NFCDiana Picus2017-11-201-94/+0
| | | | | | | | Remove some of the instruction selector tests for binary operators (and, or, xor). These are all derived from the same kind of TableGen pattern, AsI1_bin_irs, so there's no point in testing all of them. llvm-svn: 318642
* [ARM] Use dwarf exception handling on MinGWMartin Storsjo2017-11-171-0/+49
| | | | | | | | | | | | | | | Enabling and using dwarf exceptions seems like an easier path to take, than to make the COFF/ARM backend output EHABI directives. Previously, no EH model was enabled at all on this target. There's no point in setting UseIntegratedAssembler to false since GNU binutils doesn't support Windows on ARM, and since we don't need to support external assembler, we don't need to use register numbers in cfi directives. Differential Revision: https://reviews.llvm.org/D39532 llvm-svn: 318510
* [ARM] 't' asm constraint should accept i32Yi Kong2017-11-161-1/+8
| | | | | | | | | | | | | | | | | | | | 't' constraint normally only accepts f32 operands, but for VCVT the operands can be i32. LLVM is overly restrictive and rejects asm like: float foo() { float result; __asm__ __volatile__( "vcvt.f32.s32 %[result], %[arg1]\n" : [result]"=t"(result) : [arg1]"t"(0x01020304) ); return result; } Relax the value type for 't' constraint to either f32 or i32. Differential Revision: https://reviews.llvm.org/D40137 llvm-svn: 318472
* [ARM GlobalISel] Add tests for BIC. NFCDiana Picus2017-11-161-0/+206
| | | | | | | Add instruction selector tests for BICrr and BICri, which are handled by TableGen. llvm-svn: 318398
* [ARM GlobalISel] Add tests for REVSH patterns. NFCDiana Picus2017-11-161-0/+185
| | | | | | | Add instruction selector tests for some of the REVSH patterns handled by TableGen. llvm-svn: 318393
* [DAGCombine] Enable more srl -> load combinesSam Parker2017-11-161-10/+198
| | | | | | | | | | | | Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as: (srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1]) Differential Revision: https://reviews.llvm.org/D40034 llvm-svn: 318390
* [GISel]: Rework legalization algorithm for better elimination ofAditya Nandakumar2017-11-143-78/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. llvm-svn: 318210
* ARM: correctly update CFG when splitting BB to fix branch.Tim Northover2017-11-141-0/+64
| | | | | | | | | | | | Because the block-splitting code is multi-purpose, we have to meddle with the branches when using it to fixup a conditional branch destination. We got the code right, but forgot to update the CFG so the verifier complained when expensive checks were on. Probably harmless since constant-islands comes so late, but best to fix it anyway. llvm-svn: 318148
* [ARM GlobalISel] Remove C++ code for G_CONSTANTDiana Picus2017-11-142-4/+65
| | | | | | | | | | Get rid of the handwritten instruction selector code for handling G_CONSTANT. This code wasn't checking all the preconditions correctly anyway, so it's better to leave it to TableGen, which can handle at least some cases correctly (e.g. MOVi, MOVi16, folding into binary operations). Also add tests to cover those cases. llvm-svn: 318146
* [ARM] Fix incorrect conversion of a tail call to an ordinary callMomchil Velikov2017-11-142-44/+55
| | | | | | | | | | | | | | | | | | | When we emit a tail call for Armv8-M, but then discover that the caller needs to save/restore `LR`, we convert the tail call to an ordinary one, since restoring `LR` takes extra instructions, which may negate the benefits of the tail call. If the callee, however, takes stack arguments, this conversion is incorrect, since nothing has been done to pass the stack arguments. Thus the patch reverts https://reviews.llvm.org/rL294000 Also, we improve the instruction sequence for popping `LR` in the case when we couldn't immediately find a scratch low register, but we can use as a temporary one of the callee-saved low registers and restore `LR` before popping other callee-saves. Differential Revision: https://reviews.llvm.org/D39599 llvm-svn: 318143
* [arm] Fix Unnecessary reloads from GOT.Evgeniy Stepanov2017-11-132-2/+32
| | | | | | | | | | | | Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
* [ARM GlobalISel] Update legalizer testDiana Picus2017-11-131-130/+162
| | | | | | | | | | | | Make one of the legalizer tests a bit more robust by making sure all values we're interested in are used (either in a store or a return) and by using loads instead of constants for obtaining values on fewer than 32 bits. This should make the test less fragile to changes in the legalize combiner, since those loads are legal (as opposed to the constants, which were being widened and thus produced opportunities for the legalize combiner). llvm-svn: 318047
* [ARM] Place jump table as the first operand in additionsMomchil Velikov2017-11-133-7/+6
| | | | | | | | | | | | When generating table jump code for switch statements, place the jump table label as the first operand in the various addition instructions in order to enable addressing mode selectors to better match index computation and possibly fold them into the addressing mode of the table entry load instruction. Differential revision: https://reviews.llvm.org/D39752 llvm-svn: 318033
* [GlobalISel] Enable legalizing non-power-of-2 sized types.Kristof Beyls2017-11-071-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes the interface of how targets describe how to legalize, see the below description. 1. Interface for targets to describe how to legalize. In GlobalISel, the API in the LegalizerInfo class is the main interface for targets to specify which types are legal for which operations, and what to do to turn illegal type/operation combinations into legal ones. For each operation the type sizes that can be legalized without having to change the size of the type are specified with a call to setAction. This isn't different to how GlobalISel worked before. For example, for a target that supports 32 and 64 bit adds natively: for (auto Ty : {s32, s64}) setAction({G_ADD, 0, s32}, Legal); or for a target that needs a library call for a 32 bit division: setAction({G_SDIV, s32}, Libcall); The main conceptual change to the LegalizerInfo API, is in specifying how to legalize the type sizes for which a change of size is needed. For example, in the above example, how to specify how all types from i1 to i8388607 (apart from s32 and s64 which are legal) need to be legalized and expressed in terms of operations on the available legal sizes (again, i32 and i64 in this case). Before, the implementation only allowed specifying power-of-2-sized types (e.g. setAction({G_ADD, 0, s128}, NarrowScalar). A worse limitation was that if you'd wanted to specify how to legalize all the sized types as allowed by the LLVM-IR LangRef, i1 to i8388607, you'd have to call setAction 8388607-3 times and probably would need a lot of memory to store all of these specifications. Instead, the legalization actions that need to change the size of the type are specified now using a "SizeChangeStrategy". For example: setLegalizeScalarToDifferentSizeStrategy( G_ADD, 0, widenToLargerAndNarrowToLargest); This example indicates that for type sizes for which there is a larger size that can be legalized towards, do it by Widening the size. For example, G_ADD on s17 will be legalized by first doing WidenScalar to make it s32, after which it's legal. The "NarrowToLargest" indicates what to do if there is no larger size that can be legalized towards. E.g. G_ADD on s92 will be legalized by doing NarrowScalar to s64. Another example, taken from the ARM backend is: for (unsigned Op : {G_SDIV, G_UDIV}) { setLegalizeScalarToDifferentSizeStrategy(Op, 0, widenToLargerTypesUnsupportedOtherwise); if (ST.hasDivideInARMMode()) setAction({Op, s32}, Legal); else setAction({Op, s32}, Libcall); } For this example, G_SDIV on s8, on a target without a divide instruction, would be legalized by first doing action (WidenScalar, s32), followed by (Libcall, s32). The same principle is also followed for when the number of vector lanes on vector data types need to be changed, e.g.: setAction({G_ADD, LLT::vector(8, 8)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(16, 8)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(4, 16)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(8, 16)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(2, 32)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(4, 32)}, LegalizerInfo::Legal); setLegalizeVectorElementToDifferentSizeStrategy( G_ADD, 0, widenToLargerTypesUnsupportedOtherwise); As currently implemented here, vector types are legalized by first making the vector element size legal, followed by then making the number of lanes legal. The strategy to follow in the first step is set by a call to setLegalizeVectorElementToDifferentSizeStrategy, see example above. The strategy followed in the second step "moreToWiderTypesAndLessToWidest" (see code for its definition), indicating that vectors are widened to more elements so they map to natively supported vector widths, or when there isn't a legal wider vector, split the vector to map it to the widest vector supported. Therefore, for the above specification, some example legalizations are: * getAction({G_ADD, LLT::vector(3, 3)}) returns {WidenScalar, LLT::vector(3, 8)} * getAction({G_ADD, LLT::vector(3, 8)}) then returns {MoreElements, LLT::vector(8, 8)} * getAction({G_ADD, LLT::vector(20, 8)}) returns {FewerElements, LLT::vector(16, 8)} 2. Key implementation aspects. How to legalize a specific (operation, type index, size) tuple is represented by mapping intervals of integers representing a range of size types to an action to take, e.g.: setScalarAction({G_ADD, LLT:scalar(1)}, {{1, WidenScalar}, // bit sizes [ 1, 31[ {32, Legal}, // bit sizes [32, 33[ {33, WidenScalar}, // bit sizes [33, 64[ {64, Legal}, // bit sizes [64, 65[ {65, NarrowScalar} // bit sizes [65, +inf[ }); Please note that most of the code to do the actual lowering of non-power-of-2 sized types is currently missing, this is just trying to make it possible for targets to specify what is legal, and how non-legal types should be legalized. Probably quite a bit of further work is needed in the actual legalizing and the other passes in GlobalISel to support non-power-of-2 sized types. I hope the documentation in LegalizerInfo.h and the examples provided in the various {Target}LegalizerInfo.cpp and LegalizerInfoTest.cpp explains well enough how this is meant to be used. This drops the need for LLT::{half,double}...Size(). Differential Revision: https://reviews.llvm.org/D30529 llvm-svn: 317560
* [globalisel][tablegen] Skip src child predicatesDiana Picus2017-11-031-0/+35
| | | | | | | | | | | | | | | | | | The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 llvm-svn: 317313
* [ARM] and, or, xor and add with shl combineSam Parker2017-11-021-0/+173
| | | | | | | | | | | | | | | | | | | The generic dag combiner will fold: (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2) This can create constants which are too large to use as an immediate. Many ALU operations are also able of performing the shl, so we can unfold the transformation to prevent a mov imm instruction from being generated. Other patterns, such as b + ((a << 1) | 510), can also be simplified in the same manner. Differential Revision: https://reviews.llvm.org/D38084 llvm-svn: 317197
* Revert r313618 "[ARM] Use ADDCARRY / SUBCARRY"Roger Ferrer Ibanez2017-11-013-151/+15
| | | | | | That change causes PR35103, so reverting until I figure it out. llvm-svn: 317092
* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-304-0/+225
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* [ARM GlobalISel] Fixup r316572. NFCDiana Picus2017-10-301-9/+0
| | | | | | Just missed a few spots... llvm-svn: 316897
* [ARM GlobalISel] Remove redundant testcases. NFCDiana Picus2017-10-251-53/+0
| | | | | | | | Remove the G_FADD testcases from arm-legalizer.mir, they are covered by arm-legalizer-fp.mir (I probably forgot to delete them when I created that test). llvm-svn: 316573
* [ARM GlobalISel] Update test after r316479. NFCDiana Picus2017-10-251-58/+11
| | | | | | | No need to check register classes in the register block anymore, since we can now much more conveniently check them at their def. llvm-svn: 316572
* [ARM GlobalISel] Fix call opcodesDiana Picus2017-10-257-159/+163
| | | | | | | | We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570
* [ARM GlobalISel] Split test into 3. NFCDiana Picus2017-10-253-499/+502
| | | | | | | | | | | Separate the test cases that deal with calls from the rest of the IR Translator tests. We split into 2 different files, one for testing parameter and result lowering, and one for testing the various different kinds of calls that can occur (BL, BLX, BX_CALL etc). llvm-svn: 316569
* [ARM] Swap cmp operands for automatic shiftsSam Parker2017-10-251-0/+154
| | | | | | | | | | Swap the compare operands if the lhs is a shift and the rhs isn't, as in arm and T2 the shift can be performed by the compare for its second operand. Differential Revision: https://reviews.llvm.org/D39004 llvm-svn: 316562
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-2412-1321/+1319
| | | | | | | | | | | | | | | | | | | | | | | | | | This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
* [GISel][ARM]: Fix illegal Generic copies in testsAditya Nandakumar2017-10-234-227/+382
| | | | | | | This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316388
* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-221-3/+7
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-201-0/+3
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* [ARM GlobalISel] Fix liveins in test. NFCDiana Picus2017-10-191-2/+2
| | | | llvm-svn: 316155
* [ARM GlobalISel] Remove redundant testsDiana Picus2017-10-192-548/+0
| | | | | | | These test cases don't really add anything that isn't covered by other tests as well, so we can safely remove them. llvm-svn: 316154
* Canonicalize a large number of mir tests using update_mir_test_checksJustin Bogner2017-10-181-650/+403
| | | | | | | | | | This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
* [GISel]: Fix generation of illegal COPYs during CallLoweringAditya Nandakumar2017-10-091-26/+52
| | | | | | | | | | | We end up creating COPY's that are either truncating/extending and this should be illegal. https://reviews.llvm.org/D37640 Patch for X86 and ARM by igorb, rovka llvm-svn: 315240
* [ARM] GlobalISel: Make tests less strictDiana Picus2017-10-062-43/+12
| | | | | | | These are intended as integration tests, so they shouldn't be too specific about what they're checking. llvm-svn: 315083
* [ARM] GlobalISel: Select shiftsDiana Picus2017-10-061-0/+103
| | | | | | | | | Unfortunately TableGen doesn't handle this yet: Unable to deduce gMIR opcode to handle Src (which is a leaf). Just add some temporary hand-written code to generate the proper MOVsr. llvm-svn: 315071
* [ARM] GlobalISel: Map shift operands to GPRsDiana Picus2017-10-061-0/+82
| | | | llvm-svn: 315067
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