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* ARM: add intrinsics for the v8 ldaex/stlexTim Northover2014-03-261-0/+88
| | | | | | | | | We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
* Add @llvm.clear_cache builtinRenato Golin2014-03-261-0/+26
| | | | | | | | | | | | | | | | | Implementing the LLVM part of the call to __builtin___clear_cache which translates into an intrinsic @llvm.clear_cache and is lowered by each target, either to a call to __clear_cache or nothing at all incase the caches are unified. Updating LangRef and adding some tests for the implemented architectures. Other archs will have to implement the method in case this builtin has to be compiled for it, since the default behaviour is to bail unimplemented. A Clang patch is required for the builtin to be lowered into the llvm intrinsic. This will be done next. llvm-svn: 204802
* test: fix CHECK linesSaleem Abdulrasool2014-03-251-2/+2
| | | | | | Thanks to gix for pointing out that the CHECK-LABEL lines were incorrect! llvm-svn: 204700
* Fix test command line to avoid generating output file.Kevin Qin2014-03-211-1/+1
| | | | llvm-svn: 204437
* Fix an assertion caused by using inline asm with indirect register inputs.Kevin Qin2014-03-211-0/+16
| | | | llvm-svn: 204425
* Fix PR19136: [ARM] Fix Folding SP Update into vpush/vpopWeiming Zhao2014-03-201-0/+31
| | | | | | | | | | | Sicne MBB->computeRegisterLivenes() returns Dead for sub regs like s0, d0 is used in vpop instead of updating sp, which causes s0 dead before its use. This patch checks the liveness of each subreg to make sure the reg is actually dead. llvm-svn: 204411
* [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by ↵Hao Liu2014-03-201-0/+59
| | | | | | treating DPair as QPR. llvm-svn: 204304
* Remove the linker_private and linker_private_weak linkages.Rafael Espindola2014-03-132-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These linkages were introduced some time ago, but it was never very clear what exactly their semantics were or what they should be used for. Some investigation found these uses: * utf-16 strings in clang. * non-unnamed_addr strings produced by the sanitizers. It turns out they were just working around a more fundamental problem. For some sections a MachO linker needs a symbol in order to split the section into atoms, and llvm had no idea that was the case. I fixed that in r201700 and it is now safe to use the private linkage. When the object ends up in a section that requires symbols, llvm will use a 'l' prefix instead of a 'L' prefix and things just work. With that, these linkages were already dead, but there was a potential future user in the objc metadata information. I am still looking at CGObjcMac.cpp, but at this point I am convinced that linker_private and linker_private_weak are not what they need. The objc uses are currently split in * Regular symbols (no '\01' prefix). LLVM already directly provides whatever semantics they need. * Uses of a private name (start with "\01L" or "\01l") and private linkage. We can drop the "\01L" and "\01l" prefixes as soon as llvm agrees with clang on L being ok or not for a given section. I have two patches in code review for this. * Uses of private name and weak linkage. The last case is the one that one could think would fit one of these linkages. That is not the case. The semantics are * the linker will merge these symbol by *name*. * the linker will hide them in the final DSO. Given that the merging is done by name, any of the private (or internal) linkages would be a bad match. They allow llvm to rename the symbols, and that is really not what we want. From the llvm point of view, these objects should really be (linkonce|weak)(_odr)?. For now, just keeping the "\01l" prefix is probably the best for these symbols. If we one day want to have a more direct support in llvm, IMHO what we should add is not a linkage, it is just a hidden_symbol attribute. It would be applicable to multiple linkages. For example, on weak it would produce the current behavior we have for objc metadata. On internal, it would be equivalent to private (and we should then remove private). llvm-svn: 203866
* Cleanup: Remove use of old "-enable-correct-eh-support" option from a testMark Seaborn2014-03-131-1/+1
| | | | | | | | | | | | | This option enables LowerInvoke's obsolete SJLJ EH support, but the target used in this test (ARM Darwin) no longer uses the LowerInvoke pass, so the option has no effect here. This target currently uses the newer SjLjEHPrepare pass instead. This cleanup will help with removing "-enable-correct-eh-support". Differential Revision: http://llvm-reviews.chandlerc.com/D3064 llvm-svn: 203810
* [ARM] Use symbolic register names in .cfi directives only with IAS (PR19110)Hans Wennborg2014-03-133-145/+168
| | | | | | | | | | This is a follow-up to r203635. Saleem pointed out that since symbolic register names are much easier to read, it would be good if we could turn them off only when we really need to because we're using an external assembler. Differential Revision: http://llvm-reviews.chandlerc.com/D3056 llvm-svn: 203806
* ARM: correct Dwarf output for non-contiguous VFP saves.Tim Northover2014-03-122-3/+47
| | | | | | | | | | | | | | | | | | When the list of VFP registers to be saved was non-contiguous (so multiple vpush/vpop instructions were needed) these were being ordered oddly, as in: vpush {d8, d9} vpush {d11} This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be broken). This switches the order of vpush/vpop (in both prologue and epilogue, obviously) so that the Dwarf locations are correct again. rdar://problem/16264856 llvm-svn: 203655
* [ARM] Use DWARF register numbers for CFI directives in ELF assemblyHans Wennborg2014-03-123-145/+145
| | | | | | | | | | | | | | It seems gas can't handle CFI directives with VFP register names ("d12", etc.). This broke us trying to build Chromium for Android after 201423. A gas bug has been filed: https://sourceware.org/bugzilla/show_bug.cgi?id=16694 compnerd suggested making this conditional on whether we're using the integrated assembler or not. I'll look into that in a follow-up patch. Differential Revision: http://llvm-reviews.chandlerc.com/D3049 llvm-svn: 203635
* ARM: honour -f{no-,}optimize-sibling-callsSaleem Abdulrasool2014-03-111-0/+21
| | | | | | | | | | | Use the options in the ARMISelLowering to control whether tail calls are optimised or not. Previously, this option was entirely ignored on the ARM target and only honoured on x86. This option is mostly useful in profiling scenarios. The default remains that tail call optimisations will be applied. llvm-svn: 203577
* ARM: remove ancient -arm-tail-calls optionSaleem Abdulrasool2014-03-117-12/+12
| | | | | | | | This option is from 2010, designed to work around a linker issue on Darwin for ARM. According to grosbach this is no longer an issue and this option can safely be removed. llvm-svn: 203576
* ARM: enable tail call optimisation on Thumb 2Saleem Abdulrasool2014-03-115-11/+11
| | | | | | | | | | | | Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-113-6/+6
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* Fix undefined behavior in vector shift tests.Matt Arsenault2014-03-112-33/+33
| | | | | | These were all shifting the same amount as the bitwidth. llvm-svn: 203519
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-072-4/+4
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* ARM: Correctly align arguments after a byval struct is passed on the stackOliver Stannard2014-03-053-5/+119
| | | | llvm-svn: 202985
* Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can nowAdrian Prantl2014-02-273-7/+14
| | | | | | | | | | scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
* Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets.Daniel Sanders2014-02-261-1/+1
| | | | | | | | | | | | | | | | | Summary: Fixes an issue where a test attempts to use -mcpu=cortex-a15 on non-ARM targets. This triggers an assertion on MIPS since it doesn't know what ABI to use by default for unrecognized processors. Reviewers: rengolin Reviewed By: rengolin CC: llvm-commits, aemerson, rengolin Differential Revision: http://llvm-reviews.chandlerc.com/D2876 llvm-svn: 202256
* Keep the link register for uwtable.Logan Chien2014-02-251-0/+17
| | | | | | | | | | | The function with uwtable attribute might be visited by the stack unwinder, thus the link register should be considered as clobbered after the execution of the branch and link instruction (i.e. the definition of the machine instruction can't be ignored) even when the callee function are marked with noreturn. llvm-svn: 202165
* Use 16 byte stack alignment for NaCl on ARMMark Seaborn2014-02-161-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's ARM ABI uses 16 byte stack alignment, so set that in ARMSubtarget.cpp. Using 16 byte alignment exposes an issue in code generation in which a varargs function leaves a 4 byte gap between the values of r1-r3 saved to the stack and the following arguments that were passed on the stack. (Previously, this code only needed to support 4 byte and 8 byte alignment.) With this issue, llc generated: varargs_func: sub sp, sp, #16 push {lr} sub sp, sp, #12 add r0, sp, #16 // Should be 20 stm r0, {r1, r2, r3} ldr r0, .LCPI0_0 // Address of va_list add r1, sp, #16 str r1, [r0] bl external_func Fix the bug by checking for "Align > 4". Also simplify the code by using OffsetToAlignment(), and update comments. Differential Revision: http://llvm-reviews.chandlerc.com/D2677 llvm-svn: 201497
* Fix more broken CHECK linesNico Rieck2014-02-161-1/+1
| | | | llvm-svn: 201493
* Add extra CHECK prefix to tests with explicit prefixNico Rieck2014-02-161-4/+4
| | | | | | | These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. llvm-svn: 201492
* Fix broken CHECK linesNico Rieck2014-02-164-17/+17
| | | | llvm-svn: 201479
* Generate the DWARF stack frame decode operations in the function prologue ↵Artyom Skrobov2014-02-148-8/+899
| | | | | | | | for ARM/Thumb functions. Patch by Keith Walker! llvm-svn: 201423
* Add triples to try to fix the windows bots.Rafael Espindola2014-02-131-2/+2
| | | | llvm-svn: 201345
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-139-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* ARM: remove floating-point patterns for @llvm.arm.neon.vabsTim Northover2014-02-131-4/+4
| | | | | | | The front-end is now generating the generic @llvm.fabs for this operation now, so the extra patterns are no longer needed. llvm-svn: 201314
* Pass edges weights to MachineBasicBlock::addSuccessor in TailDuplicatePass toAkira Hatanaka2014-02-121-0/+52
| | | | | | | | preserve branch probability information. <rdar://problem/15893208> llvm-svn: 201245
* Revert r201237+r201238: Demote EmitRawText call in ↵Daniel Sanders2014-02-128-9/+9
| | | | | | | | AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call It introduced multiple test failures in the buildbots. llvm-svn: 201241
* Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-128-9/+9
| | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201237
* Tweak ARM fastcc by adopting these two AAPCS rules:Evan Cheng2014-02-111-0/+40
| | | | | | | | | | | | | | * CPRCs may be allocated to co-processor registers or the stack – they may never be allocated to core registers * When a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable The difference is only noticeable in rare cases where there are a large number of floating point arguments (e.g. 7 doubles + additional float, double arguments). Although it's probably still better to avoid vmov as it can cause stalls in some older ARM cores. The other, more subtle benefit, is to minimize difference between the various calling conventions. rdar://16039676 llvm-svn: 201193
* ARM: use natural LLVM IR for vshll instructionsTim Northover2014-02-101-33/+66
| | | | | | | | Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. llvm-svn: 201093
* ARM: r12 is callee-saved for interrupt handlersOliver Stannard2014-02-101-10/+11
| | | | | | | For A- and R-class processors, r12 is not normally callee-saved, but is for interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker". llvm-svn: 201089
* ARM: use LLVM IR to represent the vshrn operationTim Northover2014-02-102-12/+43
| | | | | | | | | | vshrn is just the combination of a right shift and a truncate (and the limits on the immediate value actually mean the signedness of the shift doesn't matter). Using that representation allows us to get rid of an ARM-specific intrinsic, share more code with AArch64 and hopefully get better code out of the mid-end optimisers. llvm-svn: 201085
* Fix Darwin bots from EHABI changeRenato Golin2014-02-071-2/+1
| | | | llvm-svn: 200990
* Remove -arm-disable-ehabi optionRenato Golin2014-02-071-1/+2
| | | | llvm-svn: 200988
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-071-0/+22
| | | | | | | | | | | | According to the AAPCS, when a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable. I have also modified the rules for allocating non-CPRCs to the stack, to make it more explicit that all GPRs must be made unavailable. I cannot think of a case where the old version would produce incorrect answers, so there is no test for this. llvm-svn: 200970
* PGO branch weight: fix PR18752.Manman Ren2014-02-071-0/+62
| | | | | | | Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors by getting the weights before removing a successor. llvm-svn: 200958
* Fix PR18345: ldr= pseudo instruction produces incorrect code when using in ↵David Peixotto2014-02-041-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | inline assembly This patch fixes the ldr-pseudo implementation to work when used in inline assembly. The fix is to move arm assembler constant pools from the ARMAsmParser class to the ARMTargetStreamer class. Previously we kept the assembler generated constant pools in the ARMAsmParser object. This does not work for inline assembly because a new parser object is created for each blob of inline assembly. This patch moves the constant pools to the ARMTargetStreamer class so that the constant pool will remain alive for the entire code generation process. An ARMTargetStreamer class is now required for the arm backend. There was no existing implementation for MachO, only Asm and ELF. Instead of creating an empty MachO subclass, we decided to make the ARMTargetStreamer a non-abstract class and provide default (llvm_unreachable) implementations for the non constant-pool related methods. Differential Revision: http://llvm-reviews.chandlerc.com/D2638 llvm-svn: 200777
* ARM & AArch64: merge NEON absolute compare intrinsicsTim Northover2014-02-042-8/+8
| | | | | | | | There was an extremely confusing proliferation of LLVM intrinsics to implement the vacge & vacgt instructions. This combines them all into two polymorphic intrinsics, shared across both backends. llvm-svn: 200768
* ARM: fix fast-isel assertion failureTim Northover2014-02-041-0/+11
| | | | | | | | | Missing braces on if meant we inserted both ARM and Thumb load for a litpool entry. This didn't end well. rdar://problem/15959157 llvm-svn: 200752
* DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer ↵David Blaikie2014-02-044-6/+6
| | | | | | | | | | | emits zero-length arrays as {i32 0} A bunch of test cases needed to be cleaned up for this, many my fault - when implementid imported modules I updated test cases by simply duplicating the prior metadata field - which wasn't always the empty metadata entry. llvm-svn: 200731
* AArch64 & ARM: refactor crypto intrinsics to take scalarsTim Northover2014-02-031-28/+30
| | | | | | | | | | | | Some of the SHA instructions take a scalar i32 as one argument (largely because they work on 160-bit hash fragments). This wasn't reflected in the IR previously, with ARM and AArch64 choosing different types (<4 x i32> and <1 x i32> respectively) which was ugly. This makes all the affected intrinsics take a uniform "i32", allowing them to become non-polymorphic at the same time. llvm-svn: 200706
* [stackprotector] Implement the sspstrong rules for stack layout.Josh Magee2014-02-011-0/+321
| | | | | | | | | | | | | | | | | | This changes the PrologueEpilogInserter and LocalStackSlotAllocation passes to follow the extended stack layout rules for sspstrong and sspreq. The sspstrong layout rules are: 1. Large arrays and structures containing large arrays (>= ssp-buffer-size) are closest to the stack protector. 2. Small arrays and structures containing small arrays (< ssp-buffer-size) are 2nd closest to the protector. 3. Variables that have had their address taken are 3rd closest to the protector. Differential Revision: http://llvm-reviews.chandlerc.com/D2546 llvm-svn: 200601
* PGO branch weight: update edge weights in SelectionDAGBuilder.Manman Ren2014-01-311-1/+1
| | | | | | | | | | | | | | | | When converting from "or + br" to two branches, or converting from "and + br" to two branches, we correctly update the edge weights of the two branches. The previous attempt at r200431 was reverted at r200434 because of two testing case failures. I modified my patch a little, but forgot to re-run "make check-all". Testing case CodeGen/ARM/lsr-unfolded-offset.ll is updated because of the patch's impact on branch probability which causes changes in spill placement. llvm-svn: 200502
* Reenable ARM EHABI on Android.Evgeniy Stepanov2014-01-301-0/+16
| | | | | | Broken in r200388. llvm-svn: 200466
* PGO branch weight: update edge weights in IfConverter.Manman Ren2014-01-291-0/+42
| | | | | | | | | | | | | This commit only handles IfConvertTriangle. To update edge weights of a successor, one interface is added to MachineBasicBlock: /// Set successor weight of a given iterator. setSuccWeight(succ_iterator I, uint32_t weight) An existing testing case test/CodeGen/Thumb2/v8_IT_5.ll is updated, since we now correctly update the edge weights, the cold block is placed at the end of the function and we jump to the cold block. llvm-svn: 200428
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