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* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-221-2/+14
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-221-0/+14
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* ARM: correct bundle generation for MOV32T relocationsSaleem Abdulrasool2014-05-213-3/+31
| | | | | | | | | | | | | | | | | | | | | | | Although the previous code would construct a bundle and add the correct elements to it, it would not finalise the bundle. This resulted in the InternalRead markers not being added to the MachineOperands nor, more importantly, the externally visible defs to the bundle itself. So, although the bundle was not exposing the def, the generated code would be correct because there was no optimisations being performed. When optimisations were enabled, the post register allocator would kick in, and the hazard recognizer would reorder operations around the load which would define the value being operated upon. Rather than manually constructing the bundle, simply construct and finalise the bundle via the finaliseBundle call after both MIs have been emitted. This improves the code generation with optimisations where IMAGE_REL_ARM_MOV32T relocations are emitted. The changes to the other tests are the result of the bundle generation preventing the scheduler from hoisting the moves across the loads. The net effect of the generated code is equivalent, but, is much more identical to what is actually being lowered. llvm-svn: 209267
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-191-0/+8
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-182-0/+60
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* test: fix copy-paste mistakeSaleem Abdulrasool2014-05-171-1/+1
| | | | | | Accidental over-quoting of the match string. llvm-svn: 209058
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-171-0/+15
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
* Fix most of PR10367.Rafael Espindola2014-05-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the design of GlobalAlias so that it doesn't take a ConstantExpr anymore. It now points directly to a GlobalObject, but its type is independent of the aliasee type. To avoid changing all alias related tests in this patches, I kept the common syntax @foo = alias i32* @bar to mean the same as now. The cases that used to use cast now use the more general syntax @foo = alias i16, i32* @bar. Note that GlobalAlias now behaves a bit more like GlobalVariable. We know that its type is always a pointer, so we omit the '*'. For the bitcode, a nice surprise is that we were writing both identical types already, so the format change is minimal. Auto upgrade is handled by looking through the casts and no new fields are needed for now. New bitcode will simply have different types for Alias and Aliasee. One last interesting point in the patch is that replaceAllUsesWith becomes smart enough to avoid putting a ConstantExpr in the aliasee. This seems better than checking and updating every caller. A followup patch will delete getAliasedGlobal now that it is redundant. Another patch will add support for an explicit offset. llvm-svn: 209007
* DebugInfo: Assume the CU's Subprogram list only contains definitions.David Blaikie2014-05-161-1/+1
| | | | | | | | | | | DIBuilder maintains this invariant and the current DwarfDebug code could end up doing weird things if it contained declarations (such as putting the definition DIE inside a CU that contained the declaration - this doesn't seem like a good idea, so rather than adding logic to handle this case we'll just ban in for now & cross that bridge if we come to it later). llvm-svn: 209004
* Re-enable inline memcpy expansion for Thumb1.James Molloy2014-05-161-5/+23
| | | | | | Patch by Moritz Roth! llvm-svn: 208994
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-161-85/+0
| | | | | | | | | | | | This reverts commit r208934. The patch depends on aliases to GEPs with non zero offsets. That is not supported and fairly broken. The good news is that GlobalAlias is being redesigned and will have support for offsets, so this patch should be a nice match for it. llvm-svn: 208978
* ARM: add some integer/floating point conversion libcallsSaleem Abdulrasool2014-05-161-0/+74
| | | | | | | | Add some Windows on ARM specific library calls. These are provided by msvcrt, and can be used to perform integer to floating-point conversions (and vice-versa) mirroring similar functions in the RTABI. llvm-svn: 208949
* Implement global merge optimization for global variables.Jiangning Liu2014-05-151-0/+85
| | | | | | | | | | | This commit implements two command line switches -global-merge-on-external and -global-merge-aligned, and both of them are false by default, so this optimization is disabled by default for all targets. For ARM64, some back-end behaviors need to be tuned to get this optimization further enabled. llvm-svn: 208934
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-1/+1
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* ARM-BE: test files for vector argument passingChristian Pirker2014-05-142-0/+2541
| | | | | | Reviewed at http://reviews.llvm.org/D3766 llvm-svn: 208793
* Fix ARM EHABI when function has landingpad and nounwind.Logan Chien2014-05-141-0/+61
| | | | | | | | | | | | | | | | | | | | If the function has the landingpad instruction, then the handlerdata should be emitted even if the function has nouwnind attribute. Otherwise, following code will not work: void test1() noexcept { try { throw_exception(); } catch (...) { log_unexpected_exception(); } } Since the cantunwind was incorrectly emitted and the LSDA is not available. llvm-svn: 208791
* More test case for r208715.Logan Chien2014-05-141-0/+59
| | | | | | | | | | | The commit r208166 will cause some regression on ARM EHABI. This fix has been committed in r208715, and an assertion failure test case has been committed in r208770. This commit further extends the unittest so that the actual value in the handlerdata will be checked. llvm-svn: 208790
* Regression test for ARM EHABI breakage in r208166.Evgeniy Stepanov2014-05-141-0/+50
| | | | llvm-svn: 208770
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-131-0/+73
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-131-73/+0
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-131-0/+73
| | | | llvm-svn: 208689
* Fix ARM bswap16.ll test on WindowsLouis Gerbarg2014-05-121-2/+2
| | | | | | | Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. llvm-svn: 208638
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-121-0/+42
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* ARM: Implement big endian bit-conversion for NEON typeChristian Pirker2014-05-123-3/+395
| | | | llvm-svn: 208538
* Fix ARM intrinsics-overflow.ll test on WindowsReid Kleckner2014-05-091-1/+1
| | | | | | | Windows on ARM only supports thumb mode execution, so we have to explicitly pick some non-Windows OS to test ARM mode codegen. llvm-svn: 208448
* Add custom lowering for add/sub with overflow intrinsics to ARMLouis Gerbarg2014-05-091-0/+57
| | | | | | | | | | | | | This patch adds support to ARM for custom lowering of the llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful for handling idiomatic saturating math functions as generated by InstCombineCompare. Test cases included. rdar://14853450 llvm-svn: 208435
* Attempt to pacify the bots - this commit requires asserts.James Molloy2014-05-091-0/+1
| | | | llvm-svn: 208424
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-092-0/+257
| | | | | | | | | | When using the ARM AAPCS, HFAs (Homogeneous Floating-point Aggregates) must be passed in a block of consecutive floating-point registers, or on the stack. This means that unused floating-point registers cannot be back-filled with part of an HFA, however this can currently happen. This patch, along with the corresponding clang patch (http://reviews.llvm.org/D3083) prevents this. llvm-svn: 208413
* ARM: support PIC on Windows on ARMSaleem Abdulrasool2014-05-091-0/+16
| | | | | | | | Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. llvm-svn: 208385
* test/CodeGen: Check that the correct register is used in a storeJustin Bogner2014-05-081-3/+3
| | | | | | | | | This tightens up r208351 to ensure that a store is fed with the correct value. Thanks to Quentin Colombet for spotting this! llvm-svn: 208368
* Make a CodeGen test more robust against vector register selectionJustin Bogner2014-05-081-20/+19
| | | | llvm-svn: 208351
* test: fix test on WindowsSaleem Abdulrasool2014-05-081-3/+2
| | | | | | | | When building on Windows, the default target is Windows. Windows on ARM does not support ARM mode compilation, resulting in test failures. Simply specify a triple to ensure that we are testing the correct behaviour. llvm-svn: 208340
* ARM big endian function argument passingChristian Pirker2014-05-088-129/+382
| | | | llvm-svn: 208316
* Allow using normal .eh_frame based unwinding on ARM. Use the sameJoerg Sonnenberger2014-05-072-0/+290
| | | | | | encodings as x86. Use this exception model for NetBSD. llvm-svn: 208166
* ARM: fix WoA PEI instruction selectionSaleem Abdulrasool2014-05-071-0/+27
| | | | | | | | | | | The ARM::BLX instruction is an ARM mode instruction. The Windows on ARM target is limited to Thumb instructions. Correctly use the thumb mode tBLXr instruction. This would manifest as an errant write into the object file as the instruction is 4-bytes in length rather than 2. The result would be a corrupted object file that would eventually result in an executable that would crash at runtime. llvm-svn: 208152
* If a function needs a frame pointer, but r11 (aka fp) has not been used,Joerg Sonnenberger2014-05-065-36/+38
| | | | | | | | remove it from the list of unspilled registers. Otherwise the following attempt to keep the stack aligned by picking an extra GPR register to spill will not work as it picks up r11. llvm-svn: 208129
* Implememting named register intrinsicsRenato Golin2014-05-063-0/+52
| | | | | | | | | | | This patch implements the infrastructure to use named register constructs in programs that need access to specific registers (bare metal, kernels, etc). So far, only the stack pointer is supported as a technology preview, but as it is, the intrinsic can already support all non-allocatable registers from any architecture. llvm-svn: 208104
* CodeGen: correct memset emittance for WoASaleem Abdulrasool2014-05-041-0/+18
| | | | | | | | Windows on ARM does not conform to AEABI. However, memset would be emitted using the AEABI signature, resulting in inverted parameters. Handle this special case appropriately. llvm-svn: 207943
* CodeGen: strengthen WoA AEABI avoidance testsSaleem Abdulrasool2014-05-041-0/+22
| | | | | | Add additional test cases for WoA AEABI avoidance checking. llvm-svn: 207942
* ARM: support stack probe emission for Windows on ARMSaleem Abdulrasool2014-04-301-0/+24
| | | | | | | | | | | | | | | | | This introduces the stack lowering emission of the stack probe function for Windows on ARM. The stack on Windows on ARM is a dynamically paged stack where any page allocation which crosses a page boundary of the following guard page will cause a page fault. This page fault must be handled by the kernel to ensure that the page is faulted in. If this does not occur and a write access any memory beyond that, the page fault will go unserviced, resulting in an abnormal program termination. The watermark for the stack probe appears to be at 4080 bytes (for accommodating the stack guard canaries and stack alignment) when SSP is enabled. Otherwise, the stack probe is emitted on the page size boundary of 4096 bytes. llvm-svn: 207615
* ARM: partially handle 32-bit relocations for WoASaleem Abdulrasool2014-04-301-0/+27
| | | | | | | | | | | | | | | IMAGE_REL_ARM_MOV32T relocations require that the movw/movt pair-wise relocation is not split up and reordered. When expanding the mov32imm pseudo-instruction, create a bundle if the machine operand is referencing an address. This helps ensure that the relocatable address load is not reordered by subsequent passes. Unfortunately, this only partially handles the case as the Constant Island Pass occurs after the instructions are unbundled and does not properly handle bundles. That is a more fundamental issue with the pass itself and beyond the scope of this change. llvm-svn: 207608
* ARM: fix test after change to indirect symbol emission.Tim Northover2014-04-291-2/+4
| | | | llvm-svn: 207519
* ARM: emit hidden stubs into a proper non_lazy_symbol_pointer section.Tim Northover2014-04-291-0/+22
| | | | | | rdar://problem/16660411 llvm-svn: 207517
* ARM: remove @llvm.arm.sevlSaleem Abdulrasool2014-04-251-2/+2
| | | | | | | | This intrinsic is no longer needed with the new @llvm.arm.hint(i32) intrinsic which provides a generic, extensible manner for adding hint instructions. This functionality can now be represented as @llvm.arm.hint(i32 5). llvm-svn: 207246
* ARM: provide a new generic hint intrinsicSaleem Abdulrasool2014-04-251-0/+69
| | | | | | | | | Introduce the llvm.arm.hint(i32) intrinsic that can be used to inject hints into the instruction stream. This is particularly useful for generating IR from a compiler where the user may inject an intrinsic (e.g. __yield). These are then pattern substituted into the correct instruction which already existed. llvm-svn: 207242
* Fix test/CodeGen/arm.llReid Kleckner2014-04-231-4/+4
| | | | | | | The 'CHECK: add' line was occasionally matching against the filename, breaking the subsequent CHECK-NOT. Also use CHECK-LABEL. llvm-svn: 206936
* ARM: disable emission of __XYZvfp in soft-float environment.Tim Northover2014-04-221-0/+11
| | | | | | | | | | The point of these calls is to allow Thumb-1 code to make use of the VFP unit to perform its operations. This is not desirable with -msoft-float, since most of the reasons you'd want that apply equally to the runtime library. rdar://problem/13766161 llvm-svn: 206874
* Make FastISel::SelectInstruction return before target specific fast-isel codeAkira Hatanaka2014-04-151-0/+1
| | | | | | | | | | | handles Intrinsic::trap if TargetOptions::TrapFuncName is set. This fixes a bug in which the trap function was not taken into consideration when a program was compiled without optimization (at -O0). <rdar://problem/16291933> llvm-svn: 206323
* Fix a bug in which BranchProbabilityInfo wasn't setting branch weights of ↵Akira Hatanaka2014-04-141-1/+2
| | | | | | | | | | | | basic blocks inside loops correctly. Previously, BranchProbabilityInfo::calcLoopBranchHeuristics would determine the weights of basic blocks inside loops even when it didn't have enough information to estimate the branch probabilities correctly. This patch fixes the function to exit early if it doesn't see any exit edges or back edges and let the later heuristics determine the weights. This fixes PR18705 and <rdar://problem/15991090>. Differential Revision: http://reviews.llvm.org/D3363 llvm-svn: 206194
* Fix 2008-03-05-SxtInRegBug.ll so that the CHECK-NOT will not match the filename.Richard Trieu2014-04-141-0/+2
| | | | llvm-svn: 206193
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