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* Add extra checks to mvn.ll test to prevent the "f1" check from matchingRichard Trieu2014-04-121-1/+2
| | | | | | on a directory name instead of the function name. llvm-svn: 206104
* Add the ability to use GEPs for address sinking in CGPHal Finkel2014-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The current memory-instruction optimization logic in CGP, which sinks parts of the address computation that can be adsorbed by the addressing mode, does this by explicitly converting the relevant part of the address computation into IR-level integer operations (making use of ptrtoint and inttoptr). For most targets this is currently not a problem, but for targets wishing to make use of IR-level aliasing analysis during CodeGen, the use of ptrtoint/inttoptr is a problem for two reasons: 1. BasicAA becomes less powerful in the face of the ptrtoint/inttoptr 2. In cases where type-punning was used, and BasicAA was used to override TBAA, BasicAA may no longer do so. (this had forced us to disable all use of TBAA in CodeGen; something which we can now enable again) This (use of GEPs instead of ptrtoint/inttoptr) is not currently enabled by default (except for those targets that use AA during CodeGen), and so aside from some PowerPC subtargets and SystemZ, there should be no change in behavior. We may be able to switch completely away from the ptrtoint/inttoptr sinking on all targets, but further testing is required. I've doubled-up on a number of existing tests that are sensitive to the address sinking behavior (including some store-merging tests that are sensitive to the order of the resulting ADD operations at the SDAG level). llvm-svn: 206092
* Move the segmented stack switch to a function attributeReid Kleckner2014-04-103-17/+23
| | | | | | | | | This removes the -segmented-stacks command line flag in favor of a per-function "split-stack" attribute. Patch by Luqman Aden and Alex Crichton! llvm-svn: 205997
* ARM: yet another round of ARM test clean upsSaleem Abdulrasool2014-04-034-5/+5
| | | | llvm-svn: 205586
* ARM: update even more testsSaleem Abdulrasool2014-04-036-7/+18
| | | | | | | | | More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. llvm-svn: 205545
* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-03219-328/+550
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
* ARM: tell LLVM about zext properties of ldrexb/ldrexhTim Northover2014-04-033-20/+42
| | | | | | | | | | | | | Implementing this via ComputeMaskedBits has two advantages: + It actually works. DAGISel doesn't deal with the chains properly in the previous pattern-based solution, so they never trigger. + The information can be used in other DAG combines, as well as the trivial "get rid of truncs". For example if the trunc is in a different basic block. rdar://problem/16227836 llvm-svn: 205540
* ARM: skip cmpxchg failure barrier if ordering is monotonic.Tim Northover2014-04-032-3/+41
| | | | | | | | | | The terminal barrier of a cmpxchg expansion will be either Acquire or SequentiallyConsistent. In either case it can be skipped if the operation has Monotonic requirements on failure. rdar://problem/15996804 llvm-svn: 205535
* ARM: expand atomic ldrex/strex loops in IRTim Northover2014-04-033-233/+344
| | | | | | | | | | | | | | | | | | | | | | | | | The previous situation where ATOMIC_LOAD_WHATEVER nodes were expanded at MachineInstr emission time had grown to be extremely large and involved, to account for the subtly different code needed for the various flavours (8/16/32/64 bit, cmpxchg/add/minmax). Moving this transformation into the IR clears up the code substantially, and makes future optimisations much easier: 1. an atomicrmw followed by using the *new* value can be more efficient. As an IR pass, simple CSE could handle this efficiently. 2. Making use of cmpxchg success/failure orderings only has to be done in one (simpler) place. 3. The common "cmpxchg; did we store?" idiom can be exposed to optimisation. I intend to gradually improve this situation within the ARM backend and make sure there are no hidden issues before moving the code out into CodeGen to be shared with (at least ARM64/AArch64, though I think PPC & Mips could benefit too). llvm-svn: 205525
* [ARM] When generating a vpaddl node the input lane type is not always the ↵Silviu Baranga2014-04-031-0/+11
| | | | | | | | | | type of the add operation since extract_vector_elt can perform an extend operation. Get the input lane type from the vector on which we're performing the vpaddl operation on and extend or truncate it to the output type of the original add node. llvm-svn: 205523
* ARM: fixup tests to specify the target more explicitlySaleem Abdulrasool2014-04-0220-21/+35
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205465
* ARM: update subtarget information for Windows on ARMSaleem Abdulrasool2014-04-026-0/+71
| | | | | | | Update the subtarget information for Windows on ARM. This enables using the MC layer to target Windows on ARM. llvm-svn: 205459
* ARM: Add support for segmented stacksOliver Stannard2014-04-023-0/+377
| | | | | | Patch by Alex Crichton, ILyoan, Luqman Aden and Svetoslav. llvm-svn: 205430
* Remove duplicated DMB instructionsRenato Golin2014-04-021-0/+74
| | | | | | | | | ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. llvm-svn: 205409
* ARM: add cyclone CPU with ZeroCycleZeroing feature.Tim Northover2014-04-011-0/+70
| | | | | | | | The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
* DebugInfo: Avoid creating unnecessary/empty line tables and remove the ↵David Blaikie2014-04-012-2/+2
| | | | | | | | | | | | special case of '0' in DwarfCompileUnit::initStmtList by just always using a label difference This moves one case of raw text checking down into the MCStreamer interfaces in the form of a virtual function, even if we ultimately end up consolidating on the one-or-many line tables issue one day, this is nicer in the interim. This just generally streamlines a bunch of use cases into a common code path. llvm-svn: 205287
* ARM: add intrinsics for the v8 ldaex/stlexTim Northover2014-03-261-0/+88
| | | | | | | | | We've already got versions without the barriers, so this just adds IR-level support for generating the new v8 ones. rdar://problem/16227836 llvm-svn: 204813
* Add @llvm.clear_cache builtinRenato Golin2014-03-261-0/+26
| | | | | | | | | | | | | | | | | Implementing the LLVM part of the call to __builtin___clear_cache which translates into an intrinsic @llvm.clear_cache and is lowered by each target, either to a call to __clear_cache or nothing at all incase the caches are unified. Updating LangRef and adding some tests for the implemented architectures. Other archs will have to implement the method in case this builtin has to be compiled for it, since the default behaviour is to bail unimplemented. A Clang patch is required for the builtin to be lowered into the llvm intrinsic. This will be done next. llvm-svn: 204802
* test: fix CHECK linesSaleem Abdulrasool2014-03-251-2/+2
| | | | | | Thanks to gix for pointing out that the CHECK-LABEL lines were incorrect! llvm-svn: 204700
* Fix test command line to avoid generating output file.Kevin Qin2014-03-211-1/+1
| | | | llvm-svn: 204437
* Fix an assertion caused by using inline asm with indirect register inputs.Kevin Qin2014-03-211-0/+16
| | | | llvm-svn: 204425
* Fix PR19136: [ARM] Fix Folding SP Update into vpush/vpopWeiming Zhao2014-03-201-0/+31
| | | | | | | | | | | Sicne MBB->computeRegisterLivenes() returns Dead for sub regs like s0, d0 is used in vpop instead of updating sp, which causes s0 dead before its use. This patch checks the liveness of each subreg to make sure the reg is actually dead. llvm-svn: 204411
* [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by ↵Hao Liu2014-03-201-0/+59
| | | | | | treating DPair as QPR. llvm-svn: 204304
* Remove the linker_private and linker_private_weak linkages.Rafael Espindola2014-03-132-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These linkages were introduced some time ago, but it was never very clear what exactly their semantics were or what they should be used for. Some investigation found these uses: * utf-16 strings in clang. * non-unnamed_addr strings produced by the sanitizers. It turns out they were just working around a more fundamental problem. For some sections a MachO linker needs a symbol in order to split the section into atoms, and llvm had no idea that was the case. I fixed that in r201700 and it is now safe to use the private linkage. When the object ends up in a section that requires symbols, llvm will use a 'l' prefix instead of a 'L' prefix and things just work. With that, these linkages were already dead, but there was a potential future user in the objc metadata information. I am still looking at CGObjcMac.cpp, but at this point I am convinced that linker_private and linker_private_weak are not what they need. The objc uses are currently split in * Regular symbols (no '\01' prefix). LLVM already directly provides whatever semantics they need. * Uses of a private name (start with "\01L" or "\01l") and private linkage. We can drop the "\01L" and "\01l" prefixes as soon as llvm agrees with clang on L being ok or not for a given section. I have two patches in code review for this. * Uses of private name and weak linkage. The last case is the one that one could think would fit one of these linkages. That is not the case. The semantics are * the linker will merge these symbol by *name*. * the linker will hide them in the final DSO. Given that the merging is done by name, any of the private (or internal) linkages would be a bad match. They allow llvm to rename the symbols, and that is really not what we want. From the llvm point of view, these objects should really be (linkonce|weak)(_odr)?. For now, just keeping the "\01l" prefix is probably the best for these symbols. If we one day want to have a more direct support in llvm, IMHO what we should add is not a linkage, it is just a hidden_symbol attribute. It would be applicable to multiple linkages. For example, on weak it would produce the current behavior we have for objc metadata. On internal, it would be equivalent to private (and we should then remove private). llvm-svn: 203866
* Cleanup: Remove use of old "-enable-correct-eh-support" option from a testMark Seaborn2014-03-131-1/+1
| | | | | | | | | | | | | This option enables LowerInvoke's obsolete SJLJ EH support, but the target used in this test (ARM Darwin) no longer uses the LowerInvoke pass, so the option has no effect here. This target currently uses the newer SjLjEHPrepare pass instead. This cleanup will help with removing "-enable-correct-eh-support". Differential Revision: http://llvm-reviews.chandlerc.com/D3064 llvm-svn: 203810
* [ARM] Use symbolic register names in .cfi directives only with IAS (PR19110)Hans Wennborg2014-03-133-145/+168
| | | | | | | | | | This is a follow-up to r203635. Saleem pointed out that since symbolic register names are much easier to read, it would be good if we could turn them off only when we really need to because we're using an external assembler. Differential Revision: http://llvm-reviews.chandlerc.com/D3056 llvm-svn: 203806
* ARM: correct Dwarf output for non-contiguous VFP saves.Tim Northover2014-03-122-3/+47
| | | | | | | | | | | | | | | | | | When the list of VFP registers to be saved was non-contiguous (so multiple vpush/vpop instructions were needed) these were being ordered oddly, as in: vpush {d8, d9} vpush {d11} This led to the layout in memory being [d11, d8, d9] which is ugly and doesn't match the CFI_INSTRUCTIONs we're generating either (so Dwarf info would be broken). This switches the order of vpush/vpop (in both prologue and epilogue, obviously) so that the Dwarf locations are correct again. rdar://problem/16264856 llvm-svn: 203655
* [ARM] Use DWARF register numbers for CFI directives in ELF assemblyHans Wennborg2014-03-123-145/+145
| | | | | | | | | | | | | | It seems gas can't handle CFI directives with VFP register names ("d12", etc.). This broke us trying to build Chromium for Android after 201423. A gas bug has been filed: https://sourceware.org/bugzilla/show_bug.cgi?id=16694 compnerd suggested making this conditional on whether we're using the integrated assembler or not. I'll look into that in a follow-up patch. Differential Revision: http://llvm-reviews.chandlerc.com/D3049 llvm-svn: 203635
* ARM: honour -f{no-,}optimize-sibling-callsSaleem Abdulrasool2014-03-111-0/+21
| | | | | | | | | | | Use the options in the ARMISelLowering to control whether tail calls are optimised or not. Previously, this option was entirely ignored on the ARM target and only honoured on x86. This option is mostly useful in profiling scenarios. The default remains that tail call optimisations will be applied. llvm-svn: 203577
* ARM: remove ancient -arm-tail-calls optionSaleem Abdulrasool2014-03-117-12/+12
| | | | | | | | This option is from 2010, designed to work around a linker issue on Darwin for ARM. According to grosbach this is no longer an issue and this option can safely be removed. llvm-svn: 203576
* ARM: enable tail call optimisation on Thumb 2Saleem Abdulrasool2014-03-115-11/+11
| | | | | | | | | | | | Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-113-6/+6
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* Fix undefined behavior in vector shift tests.Matt Arsenault2014-03-112-33/+33
| | | | | | These were all shifting the same amount as the bitwidth. llvm-svn: 203519
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-072-4/+4
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* ARM: Correctly align arguments after a byval struct is passed on the stackOliver Stannard2014-03-053-5/+119
| | | | llvm-svn: 202985
* Debug info: Remove ARMAsmPrinter::EmitDwarfRegOp(). AsmPrinter can nowAdrian Prantl2014-02-273-7/+14
| | | | | | | | | | scan the register file for sub- and super-registers. No functionality change intended. (Tests are updated because the comments in the assembler output are different.) llvm-svn: 202416
* Stop test/CodeGen/ARM/a15.ll targetting non-ARM targets.Daniel Sanders2014-02-261-1/+1
| | | | | | | | | | | | | | | | | Summary: Fixes an issue where a test attempts to use -mcpu=cortex-a15 on non-ARM targets. This triggers an assertion on MIPS since it doesn't know what ABI to use by default for unrecognized processors. Reviewers: rengolin Reviewed By: rengolin CC: llvm-commits, aemerson, rengolin Differential Revision: http://llvm-reviews.chandlerc.com/D2876 llvm-svn: 202256
* Keep the link register for uwtable.Logan Chien2014-02-251-0/+17
| | | | | | | | | | | The function with uwtable attribute might be visited by the stack unwinder, thus the link register should be considered as clobbered after the execution of the branch and link instruction (i.e. the definition of the machine instruction can't be ignored) even when the callee function are marked with noreturn. llvm-svn: 202165
* Use 16 byte stack alignment for NaCl on ARMMark Seaborn2014-02-161-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NaCl's ARM ABI uses 16 byte stack alignment, so set that in ARMSubtarget.cpp. Using 16 byte alignment exposes an issue in code generation in which a varargs function leaves a 4 byte gap between the values of r1-r3 saved to the stack and the following arguments that were passed on the stack. (Previously, this code only needed to support 4 byte and 8 byte alignment.) With this issue, llc generated: varargs_func: sub sp, sp, #16 push {lr} sub sp, sp, #12 add r0, sp, #16 // Should be 20 stm r0, {r1, r2, r3} ldr r0, .LCPI0_0 // Address of va_list add r1, sp, #16 str r1, [r0] bl external_func Fix the bug by checking for "Align > 4". Also simplify the code by using OffsetToAlignment(), and update comments. Differential Revision: http://llvm-reviews.chandlerc.com/D2677 llvm-svn: 201497
* Fix more broken CHECK linesNico Rieck2014-02-161-1/+1
| | | | llvm-svn: 201493
* Add extra CHECK prefix to tests with explicit prefixNico Rieck2014-02-161-4/+4
| | | | | | | These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. llvm-svn: 201492
* Fix broken CHECK linesNico Rieck2014-02-164-17/+17
| | | | llvm-svn: 201479
* Generate the DWARF stack frame decode operations in the function prologue ↵Artyom Skrobov2014-02-148-8/+899
| | | | | | | | for ARM/Thumb functions. Patch by Keith Walker! llvm-svn: 201423
* Add triples to try to fix the windows bots.Rafael Espindola2014-02-131-2/+2
| | | | llvm-svn: 201345
* Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-139-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
* ARM: remove floating-point patterns for @llvm.arm.neon.vabsTim Northover2014-02-131-4/+4
| | | | | | | The front-end is now generating the generic @llvm.fabs for this operation now, so the extra patterns are no longer needed. llvm-svn: 201314
* Pass edges weights to MachineBasicBlock::addSuccessor in TailDuplicatePass toAkira Hatanaka2014-02-121-0/+52
| | | | | | | | preserve branch probability information. <rdar://problem/15893208> llvm-svn: 201245
* Revert r201237+r201238: Demote EmitRawText call in ↵Daniel Sanders2014-02-128-9/+9
| | | | | | | | AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call It introduced multiple test failures in the buildbots. llvm-svn: 201241
* Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove ↵Daniel Sanders2014-02-128-9/+9
| | | | | | | | | | | | | | | | | | | | | hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201237
* Tweak ARM fastcc by adopting these two AAPCS rules:Evan Cheng2014-02-111-0/+40
| | | | | | | | | | | | | | * CPRCs may be allocated to co-processor registers or the stack – they may never be allocated to core registers * When a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable The difference is only noticeable in rare cases where there are a large number of floating point arguments (e.g. 7 doubles + additional float, double arguments). Although it's probably still better to avoid vmov as it can cause stalls in some older ARM cores. The other, more subtle benefit, is to minimize difference between the various calling conventions. rdar://16039676 llvm-svn: 201193
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