| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Also set addrmode6 alignment when align==size. | Jakob Stoklund Olesen | 2011-10-27 | 1 | -2/+12 |
| | | | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160 | ||||
| * | Teach LiveInterval::isZeroLength about null SlotIndexes. | Jakob Stoklund Olesen | 2011-05-16 | 1 | -4/+4 |
| | | | | | | | | | | | | | When instructions are deleted, they leave tombstone SlotIndex entries. The isZeroLength method should ignore these null indexes. This causes RABasic to sometimes spill a callee-saved register in the abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing register allocation according to spill weight can cause more registers to be used. llvm-svn: 131436 | ||||
| * | Fix a bunch of ARM tests to be register allocation independent. | Jakob Stoklund Olesen | 2011-05-03 | 1 | -11/+11 |
| | | | | | llvm-svn: 130800 | ||||
| * | Do not lose mem_operands while lowering VLD / VST intrinsics. | Evan Cheng | 2011-04-19 | 1 | -3/+7 |
| | | | | | llvm-svn: 129738 | ||||
| * | Fix ARM tests to be register allocator independent. | Jakob Stoklund Olesen | 2011-03-31 | 1 | -1/+2 |
| | | | | | llvm-svn: 128680 | ||||
| * | Add codegen support for using post-increment NEON load/store instructions. | Bob Wilson | 2011-02-07 | 1 | -0/+53 |
| | | | | | | | | | The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. llvm-svn: 125014 | ||||
| * | Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation. | Bob Wilson | 2010-12-17 | 1 | -0/+19 |
| | | | | | | | Radar 8776599 llvm-svn: 122018 | ||||
| * | Add float patterns for Neon vld1-lane/dup and vst1-lane operations. | Bob Wilson | 2010-12-10 | 1 | -0/+18 |
| | | | | | llvm-svn: 121583 | ||||
| * | Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. | Bob Wilson | 2010-12-10 | 1 | -5/+8 |
| | | | | | | | | Alignments smaller than the total size of the memory being loaded or stored, unless the alignment is 8 bytes, are not allowed. Add tests for this, too. llvm-svn: 121506 | ||||
| * | Add codegen patterns for VST1-lane instructions. Radar 8599955. | Bob Wilson | 2010-11-03 | 1 | -1/+1 |
| | | | | | llvm-svn: 118176 | ||||
| * | Add support for alignment operands on VLD1-lane instructions. | Bob Wilson | 2010-11-01 | 1 | -10/+13 |
| | | | | | | | This is another part of the fix for Radar 8599955. llvm-svn: 117976 | ||||
| * | Add VLD1-lane testcases for quad-register types. | Bob Wilson | 2010-11-01 | 1 | -0/+27 |
| | | | | | llvm-svn: 117975 | ||||
| * | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-01 | 1 | -0/+27 |
| | | | | | llvm-svn: 117964 | ||||
| * | Support alignment for NEON vld-lane and vst-lane instructions. | Bob Wilson | 2010-10-19 | 1 | -20/+30 |
| | | | | | llvm-svn: 116776 | ||||
| * | Add alignment arguments to all the NEON load/store intrinsics. | Bob Wilson | 2010-08-27 | 1 | -42/+42 |
| | | | | | | | | Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. llvm-svn: 112271 | ||||
| * | Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, | Dan Gohman | 2010-05-03 | 1 | -12/+12 |
| | | | | | | | when the type is floating-point. llvm-svn: 102969 | ||||
| * | Fix tests for Neon load/store intrinsics to match the i8* types expected by | Bob Wilson | 2010-04-20 | 1 | -18/+36 |
| | | | | | | | | | | | the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. llvm-svn: 101840 | ||||
| * | Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. | Bob Wilson | 2009-10-08 | 1 | -0/+53 |
| | | | | | | | Also fix some copy-and-paste errors in previous changes. llvm-svn: 83590 | ||||
| * | Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. | Bob Wilson | 2009-10-08 | 1 | -0/+47 |
| | | | | | llvm-svn: 83585 | ||||
| * | Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. | Bob Wilson | 2009-10-08 | 1 | -0/+41 |
| | | | | | llvm-svn: 83568 | ||||
| * | Update NEON struct names to match llvm-gcc changes. | Bob Wilson | 2009-10-06 | 1 | -72/+72 |
| | | | | | | | (This is not required for correctness but might help with sanity.) llvm-svn: 83415 | ||||
| * | Eliminate more uses of llvm-as and llvm-dis. | Dan Gohman | 2009-09-09 | 1 | -1/+1 |
| | | | | | llvm-svn: 81293 | ||||
| * | Fix incorrect declarations of intrinsics in this test. | Bob Wilson | 2009-09-01 | 1 | -12/+12 |
| | | | | | llvm-svn: 80705 | ||||
| * | Add test for vld{234}_lane instructions. | Bob Wilson | 2009-09-01 | 1 | -0/+187 |
| llvm-svn: 80658 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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