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* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-1/+1
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>Bob Wilson2011-12-121-0/+10
| | | | | | | | | These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. llvm-svn: 146417
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+12
| | | | | | Fixes rdar://9866494 llvm-svn: 136523
* Add support for the 'j' immediate constraint. This is conditionalized onEric Christopher2011-07-011-3/+13
| | | | | | | | supporting the instruction that the constraint is for 'movw'. Part of rdar://9119939 llvm-svn: 134222
* Add support for the ARM 't' register constraint. And another testcaseEric Christopher2011-07-011-0/+20
| | | | | | | | for the 'x' register constraint. Part of rdar://9119939 llvm-svn: 134220
* Add support for the 'x' constraint.Eric Christopher2011-07-011-0/+10
| | | | | | Part of rdar://9307836 and rdar://9119939 llvm-svn: 134215
* Another possible bug. Stopgap until we can autogenerate tables andEric Christopher2011-06-031-0/+8
| | | | | | | | constraint lengths. Part of rdar://9037836 and rdar://9119939 llvm-svn: 132598
* Fix an off by one error.Eric Christopher2011-06-031-0/+9
| | | | | | Part of rdar://9037836 and rdar://9119939 llvm-svn: 132590
* Make the Uv constraint a memory operand. This doesn't solve theEric Christopher2011-06-031-0/+8
| | | | | | | | addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 llvm-svn: 132561
* Allow bitcasts between valid types of the same size and vectorEric Christopher2011-06-011-0/+10
| | | | | | | | types if the vector type is legal. Fixes rdar://9306086 llvm-svn: 132420
* Make tests register allocation independent again.Jakob Stoklund Olesen2011-04-191-1/+1
| | | | llvm-svn: 129739
* Change register allocation order for ARM VFP and NEON registers to put theBob Wilson2010-10-081-2/+2
| | | | | | | | | | | | | | | | callee-saved registers at the end of the lists. Also prefer to avoid using the low registers that are in register subclasses required by certain instructions, so that those registers will more likely be available when needed. This change makes a huge improvement in spilling in some cases. Thanks to Jakob for helping me realize the problem. Most of this patch is fixing the testsuite. There are quite a few places where we're checking for specific registers. I changed those to wildcards in places where that doesn't weaken the tests. The spill-q.ll and thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch of live values to force spills on those tests. llvm-svn: 116055
* Remove arm_apcscc from the test files. It is the default and doing thisRafael Espindola2010-06-171-2/+2
| | | | | | matches what llvm-gcc and clang now produce. llvm-svn: 106221
* Handle ARM inline asm "w" constraints with 64-bit ("d") registers.Bob Wilson2009-12-181-0/+12
| | | | | | | | The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. llvm-svn: 91649
* - Support inline asm 'w' constraint for 128-bit vector types.Evan Cheng2009-12-081-0/+13
- Also support the 'q' NEON registers asm code. llvm-svn: 90894
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