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* [GlobalISel] Translate shufflevectorVolkan Keles2017-03-211-0/+80
| | | | | | | | | | | | Reviewers: qcolombet, aditya_nandakumar, t.p.northover, javed.absar, ab, dsanders Reviewed By: javed.absar Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30962 llvm-svn: 298347
* [GlobalISel] Use the correct calling conv for callsDiana Picus2017-03-201-0/+17
| | | | | | | | | | | This commit adds a parameter that lets us pass in the calling convention of the call to CallLowering::lowerCall. This allows us to handle situations where the calling convetion of the callee is different from that of the caller. Differential Revision: https://reviews.llvm.org/D31039 llvm-svn: 298254
* [GlobalISel] Don't select trivially dead instructions.Ahmed Bougacha2017-03-191-2/+8
| | | | | | | | | | | | | | Folding instructions when selecting can cause them to become dead. Don't select these dead instructions (if they don't have other side effects, and don't define physical registers). Preserve existing tests by adding COPYs. In some tests, the G_CONSTANT vregs never get constrained to a class: the only use of the vreg was folded into another instruction, so the G_CONSTANT, now dead, never gets selected. llvm-svn: 298224
* [ARM] GlobalISel: Support SP in regbankselectDiana Picus2017-03-131-0/+35
| | | | | | | We used to hit an unreachable in getRegBankFromRegClass when dealing with the stack pointer. This commit adds support for the GPRsp reg class. llvm-svn: 297621
* GlobalISel: restrict G_EXTRACT instruction to just one operand.Tim Northover2017-03-064-12/+24
| | | | | | | A bit more painful than G_INSERT because it was more widely used, but this should simplify the handling of extract operations in most locations. llvm-svn: 297100
* [ARM] GlobalISel: Lower call params that need extensionsDiana Picus2017-03-011-17/+43
| | | | | | | | | | | | | | | | | | | | | | Lower i1, i8 and i16 call parameters by extending them before storing them on the stack. Also make sure we encode the correct, extended size in the corresponding memory operand, and that we compute the correct stack size in the end. The latter is a bit more complicated because we used to compute the stack size in the getStackAddress method, based on the Size and Offset of the parameters. However, if the last parameter is sign extended, we'd be using the wrong, non-extended size, and we'd end up with a smaller stack than we need to hold the extended value. Instead of hacking this up based on the value of Size in getStackAddress, we move our stack size handling logic to assignArg, where we have access to the CCState which knows everything we could possibly want to know about the stack. This way we don't need to duplicate any knowledge or resort to any ugly hacks. On this same occasion, update the IRTranslator test to check the sizes of the stores everywhere, not just for sign extended paramteres. llvm-svn: 296631
* [ARM] GlobalISel: Lower i32 and fp call parameters on the stackDiana Picus2017-02-281-9/+46
| | | | | | | | | | | | Lower i32, float and double parameters that need to live on the stack. This boils down to creating some G_GEPs starting from the stack pointer and storing the values there. During the process we also keep track of the stack size and use the final value in the ADJCALLSTACKDOWN/UP instructions. We currently assert for smaller types, since they usually require extensions. They will be handled in a separate patch. llvm-svn: 296473
* [ARM] GlobalISel: Select 32-bit G_CONSTANTDiana Picus2017-02-281-0/+19
| | | | | | Put it into a register by means of a MOVi. llvm-svn: 296471
* [ARM] GlobalISel: Add mapping for G_CONSTANTDiana Picus2017-02-281-0/+18
| | | | | | | Like G_FRAME_INDEX, G_CONSTANT has one register operand and one non-register operand. llvm-svn: 296469
* [ARM] GlobalISel: Legalize 32-bit constantsDiana Picus2017-02-281-0/+20
| | | | llvm-svn: 296468
* [ARM] GlobalISel: Select G_GEPDiana Picus2017-02-281-0/+29
| | | | | | At this point, G_GEP is just an add, so we treat it exactly like a G_ADD. llvm-svn: 296462
* [ARM] GlobalISel: Add reg bank mapping for G_GEPDiana Picus2017-02-281-0/+27
| | | | | | This should be the same as the mapping for G_ADD etc. llvm-svn: 296455
* [ARM] GlobalISel: Legalize G_GEP with 32-bit offsetsDiana Picus2017-02-281-0/+27
| | | | | | | At the moment we're only interested in GEPs for putting call parameters on the stack, so we'll stick to 32-bit offsets. llvm-svn: 296452
* [ARM] GlobalISel: Select G_STOREDiana Picus2017-02-241-0/+50
| | | | | | Same as selecting G_LOAD. llvm-svn: 296122
* Minor test fixDiana Picus2017-02-241-2/+2
| | | | | | The test was using a size of 8 for loading/storing pointers. It should be 4. llvm-svn: 296120
* [ARM] GlobalISel: Add reg bank mappings for storesDiana Picus2017-02-241-0/+43
| | | | | | Same as the ones for loads. llvm-svn: 296115
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-241-0/+43
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296108
* Revert "[ARM] GlobalISel: Legalize stores"Diana Picus2017-02-241-37/+0
| | | | | | This reverts commit r296103 because the test broke on one of the bots. Sorry! llvm-svn: 296104
* [ARM] GlobalISel: Legalize storesDiana Picus2017-02-241-0/+37
| | | | | | Allow the same types that we allow for loads. llvm-svn: 296103
* [ARM] GlobalISel: Lower call returnsDiana Picus2017-02-231-20/+40
| | | | | | | | Introduce a common ValueHandler for call returns and formal arguments, and inherit two different versions for handling the differences (at the moment the only difference is the way physical registers are marked as used). llvm-svn: 295973
* [ARM] GlobalISel: Lower call parameters in regsDiana Picus2017-02-231-0/+77
| | | | | | | | Add support for lowering calls with parameters than can fit into regs. Use the same ValueHandler that we used for function returns, but rename it to match its new, extended purpose. llvm-svn: 295971
* [ARM] GlobalISel: Lower calls to void() functionsDiana Picus2017-02-211-0/+23
| | | | | | | For now, we hardcode a BLX instruction, and generate an ADJCALLSTACKDOWN/UP pair with amount 0. llvm-svn: 295716
* GlobalISel: verify that generic loads & stores have a mem operand.Tim Northover2017-02-173-18/+18
| | | | | | | The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
* [ARM] GlobalISel: Use Subtarget in LegalizerDiana Picus2017-02-171-3/+5
| | | | | | | | Start using the Subtarget to make decisions about what's legal. In particular, we only mark floating point operations as legal if we have VFP2, which is something we should've done from the very start. llvm-svn: 295439
* [ARM] GlobalISel: Add end-to-end tests for doubleDiana Picus2017-02-171-0/+21
| | | | | | Test some really basic functionality through the whole GlobalISel pipeline. llvm-svn: 295438
* [ARM] GlobalISel: Select floating point loadsDiana Picus2017-02-161-0/+56
| | | | llvm-svn: 295321
* [ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACTDiana Picus2017-02-161-0/+45
| | | | | | | | Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
* [ARM] GlobalISel: Select double G_FADD and copiesDiana Picus2017-02-161-0/+34
| | | | | | Just use VADDD if available, bail out if not. llvm-svn: 295309
* [ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFPDiana Picus2017-02-161-4/+6
| | | | llvm-svn: 295308
* [ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACTDiana Picus2017-02-161-0/+32
| | | | | | | Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating point values in the soft-fp float mode. llvm-svn: 295306
* [ARM] GlobalISel: Make the FPR bank 64-bit wideDiana Picus2017-02-161-2/+34
| | | | | | | Also add mappings for single and double precision FP, and use them for G_FADD and G_LOAD. llvm-svn: 295302
* [ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOADDiana Picus2017-02-161-0/+29
| | | | | | | | For now we just mark them as legal all the time and let the other passes bail out if they can't handle it. In the future, we'll want to move more of the brains into the legalizer. llvm-svn: 295300
* [ARM] GlobalISel: Lower double precision FP argsDiana Picus2017-02-161-1/+116
| | | | | | | | | | | | | | For the hard float calling convention, we just use the D registers. For the soft-fp calling convention, we use the R registers and move values to/from the D registers by means of G_SEQUENCE/G_EXTRACT. While doing so, we make sure to honor the endianness of the target, since the CCAssignFn doesn't do that for us. For pure soft float targets, we still bail out because we don't support the libcalls yet. llvm-svn: 295295
* [ARM] GlobalISel: Lower single precision FP argsDiana Picus2017-02-092-2/+71
| | | | | | | Both for aapcscc and aapcs_vfpcc. We currently filter out soft float targets because we don't support libcalls yet. llvm-svn: 294584
* Fix test to work on swift/cyclone tooDiana Picus2017-02-081-1/+1
| | | | | | | I forgot to remove the neonfp target feature from the test, which means we'd have trouble selecting VADDS on targets that have neonfp enabled by default. llvm-svn: 294451
* [ARM] GlobalISel: Add FPR reg bankDiana Picus2017-02-083-0/+92
| | | | | | | | | | | | | Add a register bank for floating point values and select simple instructions using them (add, copies from GPR). This assumes that the hardware can cope with a single precision add (VADDS) instruction, so the legalizer will treat G_FADD as legal and the instruction selector will refuse to select if the hardware doesn't support it. In the future we'll want to be more careful about this, and legalize to libcalls if we have to use soft float. llvm-svn: 294442
* [ARM] GlobalISel: Lower pointer args and returnsDiana Picus2017-02-022-0/+67
| | | | | | | | | It is important to change the ArgInfo's type from pointer to integer, otherwise the CC assign function won't know what to do. Instead of hacking it up, we use ComputeValueVTs and introduce some of the helpers that we will need later on for lowering more complex types. llvm-svn: 293889
* [ARM] GlobalISel: Legalize loading pointersDiana Picus2017-02-022-0/+37
| | | | | | | Make it legal to load pointer values. Also check that pointers are assigned to the GPR reg bank by default. llvm-svn: 293886
* [ARM] GlobalISel: Test default banks for load results. NFC.Diana Picus2017-02-021-0/+32
| | | | | | Check that all scalars are loaded into the GPR by default. llvm-svn: 293883
* [ARM] GlobalISel: Load i1, i8 and i16 args from stackDiana Picus2017-01-263-8/+84
| | | | | | | | | | | | | Add support for loading i1, i8 and i16 arguments from the stack, with or without the ABI extension flags. When the ABI extension flags are present, we load a 4-byte value, otherwise we preserve the size of the load and let the instruction selector replace it with a LDRB/LDRH. This generates the same thing as DAGISel. Differential Revision: https://reviews.llvm.org/D27803 llvm-svn: 293163
* [ARM] GlobalISel: Support i1 add and ABI extensionsDiana Picus2017-01-254-0/+113
| | | | | | | | | | | Add support for: * i1 add * i1 function arguments, if passed through registers * i1 returns, with ABI signext/zeroext Differential Revision: https://reviews.llvm.org/D27706 llvm-svn: 293035
* [ARM] GlobalISel: Support i8/i16 ABI extensionsDiana Picus2017-01-254-0/+141
| | | | | | | | | | | | | At the moment, this means supporting the signext/zeroext attribute on the return type of the function. For function arguments, signext/zeroext should be handled by the caller, so there's nothing for us to do until we start lowering calls. Note that this does not include support for other extensions (i8 to i16), those will be added later. Differential Revision: https://reviews.llvm.org/D27705 llvm-svn: 293034
* [ARM] GlobalISel: Add more checks to testDiana Picus2016-12-191-0/+4
| | | | llvm-svn: 290108
* [ARM] GlobalISel: Minor style fixup in testDiana Picus2016-12-191-3/+3
| | | | llvm-svn: 290107
* [ARM] GlobalISel: Lower i8 and i16 register argsDiana Picus2016-12-192-8/+52
| | | | | | | | | | | This allows lowering i8 and i16 arguments if they can fit in the registers. Note that the lowering is incomplete - ABI extensions are handled in a subsequent patch. (Last part of) Differential Revision: https://reviews.llvm.org/D27704 llvm-svn: 290106
* [ARM] GlobalISel: Allow i8 and i16 addsDiana Picus2016-12-193-5/+122
| | | | | | | | | Teach the instruction selector and legalizer that it's ok to have adds with 8 or 16-bit integers. This is the second part of https://reviews.llvm.org/D27704 llvm-svn: 290105
* [ARM] GlobalISel: Select i8 and i16 copiesDiana Picus2016-12-191-3/+60
| | | | | | | | | Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 llvm-svn: 290104
* [ARM] GlobalISel: Lower more than 4 argumentsDiana Picus2016-12-192-0/+28
| | | | | | | | | | This adds support for lowering more than 4 arguments (although still i32 only). It uses the handleAssignments / ValueHandler infrastructure extracted from the AArch64 backend in r288658. Differential Revision: https://reviews.llvm.org/D27195 llvm-svn: 290098
* [ARM] GlobalISel: Support loading from the stackDiana Picus2016-12-192-0/+62
| | | | | | | | | | Add support for selecting simple G_LOAD and G_FRAME_INDEX instructions (32-bit scalars only). This will be useful for functions that need to pass arguments on the stack. First part of https://reviews.llvm.org/D27195. llvm-svn: 290096
* [ARM] GlobalISel: Select add i32, i32Diana Picus2016-12-165-0/+125
| | | | | | | | | | | | | Add the minimal support necessary to select a function that returns the sum of two i32 values. This includes some support for argument/return lowering of i32 values through registers, as well as the handling of copy and add instructions throughout the GlobalISel pipeline. Differential Revision: https://reviews.llvm.org/D26677 llvm-svn: 289940
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