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* [ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32Diana Picus2017-12-223-0/+139
| | | | | | | Mark conversions between pointers and 32-bit scalars as legal, map them to the GPR and select to a simple COPY. llvm-svn: 321356
* [ARM GlobalISel] Support pointer constantsDiana Picus2017-12-222-0/+23
| | | | | | | | | | Pointer constants are pretty rare, since we usually represent them as integer constants and then cast to pointer. One notable exception is the null pointer constant, which is represented directly as a G_CONSTANT 0 with pointer type. Mark it as legal and make sure it is selected like any other integer constant. llvm-svn: 321354
* [ARM GlobalISel] Fix assertion in RegBankSelectDiana Picus2017-12-202-0/+56
| | | | | | | | | | | | | | | | | | | | We get an assertion in RegBankSelect for code along the lines of my_32_bit_int = my_64_bit_int, which tends to translate into a 64-bit load, followed by a G_TRUNC, followed by a 32-bit store. This appears in a couple of places in the test-suite. At the moment, the legalizer doesn't distinguish between integer and floating point scalars, so a 64-bit load will be marked as legal for targets with VFP, and so will the rest of the sequence, leading to a slightly bizarre G_TRUNC reaching RegBankSelect. Since the current support for 64-bit integers is rather immature, this patch works around the issue by explicitly handling this case in RegBankSelect and InstructionSelect. In the future, we may want to revisit this decision and make sure 64-bit integer loads are narrowed before reaching RegBankSelect. llvm-svn: 321165
* [GlobalISel] Disable GISel for big endian.Amara Emerson2017-12-112-2/+4
| | | | | | | | | | | | | This is due to PR26161 needing to be resolved before we can fix big endian bugs like PR35359. The work to split aggregates into smaller LLTs instead of using one large scalar will take some time, so in the mean time we'll fall back to SDAG. Some ARM BE tests xfailed for now as a result. Differential Revision: https://reviews.llvm.org/D40789 llvm-svn: 320388
* [ARM GlobalISel] Add test for a MOVTi16 pattern. NFCDiana Picus2017-12-111-0/+31
| | | | | | Add test for matching an OR with 0xFFFF0000 to a MOVTi16. llvm-svn: 320362
* [ARM GlobalISel] Add tests for PKHBT and PKHTBDiana Picus2017-12-111-0/+254
| | | | | | | | Test (some of) the patterns for selecting PKHBT and PKHTB. The others are just very similar to the ones we're testing and there would be little value in covering them as well. llvm-svn: 320352
* [globalisel][tablegen] Add support for specific immediates in the match patternDaniel Sanders2017-11-301-1/+1
| | | | | | This enables a few rules such as ARM's uxtb instruction. llvm-svn: 319457
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-3013-631/+631
| | | | | | | | | | | | | | output As part of the unification of the debug format and the MIR format, always use `printReg` to print all kinds of registers. Updated the tests using '_' instead of '%noreg' until we decide which one we want to be the default one. Differential Revision: https://reviews.llvm.org/D40421 llvm-svn: 319445
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-301-0/+15
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [ARM GlobalISel] Fix selecting G_BRCONDDiana Picus2017-11-292-2/+2
| | | | | | | | | | | | | When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
* [globalisel][tablegen] Fix PR35375 by sign-extending the table value to ↵Daniel Sanders2017-11-281-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | match getConstantVRegVal() Summary: From the bug report: > The problem is that it fails when trying to compare -65536 (or 4294901760) to 0xFFFF,0000. This is because the > constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non > extended 64 bit version expected by TableGen. > > In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not > sign extend. This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check. Thanks to Diana Picus for the detailed bug report. Reviewers: rovka Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40532 llvm-svn: 319252
* [ARM GlobalISel] Support G_FDIV for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | | TableGen already generates code for selecting a G_FDIV, so we only need to add a test. For the legalizer and reg bank select, we do the same thing as for the other floating point binary operations: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318915
* [ARM GlobalISel] Support G_FMUL for s32 and s64Diana Picus2017-11-233-0/+208
| | | | | | | | | | | TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910
* [ARM GlobalISel] Add comment for r318398. NFC.Diana Picus2017-11-211-0/+5
| | | | | | | Mention the purpose of the BICri tests added by r318398, as requested in post-commit review. llvm-svn: 318747
* [ARM GlobalISel] Add test for RSBri. NFCDiana Picus2017-11-201-0/+58
| | | | | | | | Add instruction selector test for RSBri, which is derived from AsI1_rbin_irs, and make sure it doesn't get mistaken for SUBri, which is derived from the very similar AsI1_bin_irs pattern. llvm-svn: 318643
* [ARM GlobalISel] Clean up binary operator tests. NFCDiana Picus2017-11-201-94/+0
| | | | | | | | Remove some of the instruction selector tests for binary operators (and, or, xor). These are all derived from the same kind of TableGen pattern, AsI1_bin_irs, so there's no point in testing all of them. llvm-svn: 318642
* [ARM GlobalISel] Add tests for BIC. NFCDiana Picus2017-11-161-0/+206
| | | | | | | Add instruction selector tests for BICrr and BICri, which are handled by TableGen. llvm-svn: 318398
* [ARM GlobalISel] Add tests for REVSH patterns. NFCDiana Picus2017-11-161-0/+185
| | | | | | | Add instruction selector tests for some of the REVSH patterns handled by TableGen. llvm-svn: 318393
* [GISel]: Rework legalization algorithm for better elimination ofAditya Nandakumar2017-11-143-78/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | artifacts along with DCE Legalization Artifacts are all those insts that are there to make the type system happy. Currently, the target needs to say all combinations of extends and truncs are legal and there's no way of verifying that post legalization, we only have *truly* legal instructions. This patch changes roughly the legalization algorithm to process all illegal insts at one go, and then process all truncs/extends that were added to satisfy the type constraints separately trying to combine trivial cases until they converge. This has the added benefit that, the target legalizerinfo can only say which truncs and extends are okay and the artifact combiner would combine away other exts and truncs. Updated legalization algorithm to roughly the following pseudo code. WorkList Insts, Artifacts; collect_all_insts_and_artifacts(Insts, Artifacts); do { for (Inst in Insts) legalizeInstrStep(Inst, Insts, Artifacts); for (Artifact in Artifacts) tryCombineArtifact(Artifact, Insts, Artifacts); } while(!Insts.empty()); Also, wrote a simple wrapper equivalent to SetVector, except for erasing, it avoids moving all elements over by one and instead just nulls them out. llvm-svn: 318210
* [ARM GlobalISel] Remove C++ code for G_CONSTANTDiana Picus2017-11-142-4/+65
| | | | | | | | | | Get rid of the handwritten instruction selector code for handling G_CONSTANT. This code wasn't checking all the preconditions correctly anyway, so it's better to leave it to TableGen, which can handle at least some cases correctly (e.g. MOVi, MOVi16, folding into binary operations). Also add tests to cover those cases. llvm-svn: 318146
* [arm] Fix Unnecessary reloads from GOT.Evgeniy Stepanov2017-11-131-2/+2
| | | | | | | | | | | | Summary: This fixes PR35221. Use pseudo-instructions to let MachineCSE hoist global address computation. Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D39871 llvm-svn: 318081
* [ARM GlobalISel] Update legalizer testDiana Picus2017-11-131-130/+162
| | | | | | | | | | | | Make one of the legalizer tests a bit more robust by making sure all values we're interested in are used (either in a store or a return) and by using loads instead of constants for obtaining values on fewer than 32 bits. This should make the test less fragile to changes in the legalize combiner, since those loads are legal (as opposed to the constants, which were being widened and thus produced opportunities for the legalize combiner). llvm-svn: 318047
* [GlobalISel] Enable legalizing non-power-of-2 sized types.Kristof Beyls2017-11-071-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes the interface of how targets describe how to legalize, see the below description. 1. Interface for targets to describe how to legalize. In GlobalISel, the API in the LegalizerInfo class is the main interface for targets to specify which types are legal for which operations, and what to do to turn illegal type/operation combinations into legal ones. For each operation the type sizes that can be legalized without having to change the size of the type are specified with a call to setAction. This isn't different to how GlobalISel worked before. For example, for a target that supports 32 and 64 bit adds natively: for (auto Ty : {s32, s64}) setAction({G_ADD, 0, s32}, Legal); or for a target that needs a library call for a 32 bit division: setAction({G_SDIV, s32}, Libcall); The main conceptual change to the LegalizerInfo API, is in specifying how to legalize the type sizes for which a change of size is needed. For example, in the above example, how to specify how all types from i1 to i8388607 (apart from s32 and s64 which are legal) need to be legalized and expressed in terms of operations on the available legal sizes (again, i32 and i64 in this case). Before, the implementation only allowed specifying power-of-2-sized types (e.g. setAction({G_ADD, 0, s128}, NarrowScalar). A worse limitation was that if you'd wanted to specify how to legalize all the sized types as allowed by the LLVM-IR LangRef, i1 to i8388607, you'd have to call setAction 8388607-3 times and probably would need a lot of memory to store all of these specifications. Instead, the legalization actions that need to change the size of the type are specified now using a "SizeChangeStrategy". For example: setLegalizeScalarToDifferentSizeStrategy( G_ADD, 0, widenToLargerAndNarrowToLargest); This example indicates that for type sizes for which there is a larger size that can be legalized towards, do it by Widening the size. For example, G_ADD on s17 will be legalized by first doing WidenScalar to make it s32, after which it's legal. The "NarrowToLargest" indicates what to do if there is no larger size that can be legalized towards. E.g. G_ADD on s92 will be legalized by doing NarrowScalar to s64. Another example, taken from the ARM backend is: for (unsigned Op : {G_SDIV, G_UDIV}) { setLegalizeScalarToDifferentSizeStrategy(Op, 0, widenToLargerTypesUnsupportedOtherwise); if (ST.hasDivideInARMMode()) setAction({Op, s32}, Legal); else setAction({Op, s32}, Libcall); } For this example, G_SDIV on s8, on a target without a divide instruction, would be legalized by first doing action (WidenScalar, s32), followed by (Libcall, s32). The same principle is also followed for when the number of vector lanes on vector data types need to be changed, e.g.: setAction({G_ADD, LLT::vector(8, 8)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(16, 8)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(4, 16)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(8, 16)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(2, 32)}, LegalizerInfo::Legal); setAction({G_ADD, LLT::vector(4, 32)}, LegalizerInfo::Legal); setLegalizeVectorElementToDifferentSizeStrategy( G_ADD, 0, widenToLargerTypesUnsupportedOtherwise); As currently implemented here, vector types are legalized by first making the vector element size legal, followed by then making the number of lanes legal. The strategy to follow in the first step is set by a call to setLegalizeVectorElementToDifferentSizeStrategy, see example above. The strategy followed in the second step "moreToWiderTypesAndLessToWidest" (see code for its definition), indicating that vectors are widened to more elements so they map to natively supported vector widths, or when there isn't a legal wider vector, split the vector to map it to the widest vector supported. Therefore, for the above specification, some example legalizations are: * getAction({G_ADD, LLT::vector(3, 3)}) returns {WidenScalar, LLT::vector(3, 8)} * getAction({G_ADD, LLT::vector(3, 8)}) then returns {MoreElements, LLT::vector(8, 8)} * getAction({G_ADD, LLT::vector(20, 8)}) returns {FewerElements, LLT::vector(16, 8)} 2. Key implementation aspects. How to legalize a specific (operation, type index, size) tuple is represented by mapping intervals of integers representing a range of size types to an action to take, e.g.: setScalarAction({G_ADD, LLT:scalar(1)}, {{1, WidenScalar}, // bit sizes [ 1, 31[ {32, Legal}, // bit sizes [32, 33[ {33, WidenScalar}, // bit sizes [33, 64[ {64, Legal}, // bit sizes [64, 65[ {65, NarrowScalar} // bit sizes [65, +inf[ }); Please note that most of the code to do the actual lowering of non-power-of-2 sized types is currently missing, this is just trying to make it possible for targets to specify what is legal, and how non-legal types should be legalized. Probably quite a bit of further work is needed in the actual legalizing and the other passes in GlobalISel to support non-power-of-2 sized types. I hope the documentation in LegalizerInfo.h and the examples provided in the various {Target}LegalizerInfo.cpp and LegalizerInfoTest.cpp explains well enough how this is meant to be used. This drops the need for LLT::{half,double}...Size(). Differential Revision: https://reviews.llvm.org/D30529 llvm-svn: 317560
* [globalisel][tablegen] Skip src child predicatesDiana Picus2017-11-031-0/+35
| | | | | | | | | | | | | | | | | | The GlobalISel TableGen backend didn't check for predicates on the source children. This caused it to generate code for ARM patterns such as SMLABB or similar, but without properly checking for the sext_16_node part of the operands. This in turn meant that we would select SMLABB instead of MLA for simple sequences such as s32 + s32 * s32, which is wrong (we want a MLA on the full operands, not just their bottom 16 bits). This patch forces TableGen to skip patterns with predicates on the src children, so it doesn't generate code for SMLABB and other similar ARM instructions at all anymore. AArch64 and X86 are not affected. Differential Revision: https://reviews.llvm.org/D39554 llvm-svn: 317313
* [GlobalISel|ARM] : Allow legalizing G_FSUBJaved Absar2017-10-304-0/+225
| | | | | | | | Adding support for VSUB. Reviewed by: @rovka Differential Revision: https://reviews.llvm.org/D39261 llvm-svn: 316902
* [ARM GlobalISel] Fixup r316572. NFCDiana Picus2017-10-301-9/+0
| | | | | | Just missed a few spots... llvm-svn: 316897
* [ARM GlobalISel] Remove redundant testcases. NFCDiana Picus2017-10-251-53/+0
| | | | | | | | Remove the G_FADD testcases from arm-legalizer.mir, they are covered by arm-legalizer-fp.mir (I probably forgot to delete them when I created that test). llvm-svn: 316573
* [ARM GlobalISel] Update test after r316479. NFCDiana Picus2017-10-251-58/+11
| | | | | | | No need to check register classes in the register block anymore, since we can now much more conveniently check them at their def. llvm-svn: 316572
* [ARM GlobalISel] Fix call opcodesDiana Picus2017-10-257-159/+163
| | | | | | | | We were generating BLX for all the calls, which was incorrect in most cases. Update ARMCallLowering to generate BL for direct calls, and BLX, BX_CALL or BMOVPCRX_CALL for indirect calls. llvm-svn: 316570
* [ARM GlobalISel] Split test into 3. NFCDiana Picus2017-10-253-499/+502
| | | | | | | | | | | Separate the test cases that deal with calls from the rest of the IR Translator tests. We split into 2 different files, one for testing parameter and result lowering, and one for testing the various different kinds of calls that can occur (BL, BLX, BX_CALL etc). llvm-svn: 316569
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-2410-1301/+1301
| | | | | | | | | | | | | | | | | | | | | | | | | | This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
* [GISel][ARM]: Fix illegal Generic copies in testsAditya Nandakumar2017-10-234-227/+382
| | | | | | | This is in preparation for a verifier check that makes sure copies are of the same size (when generic virtual registers are involved). llvm-svn: 316388
* [ARM GlobalISel] Fix liveins in test. NFCDiana Picus2017-10-191-2/+2
| | | | llvm-svn: 316155
* [ARM GlobalISel] Remove redundant testsDiana Picus2017-10-192-548/+0
| | | | | | | These test cases don't really add anything that isn't covered by other tests as well, so we can safely remove them. llvm-svn: 316154
* Canonicalize a large number of mir tests using update_mir_test_checksJustin Bogner2017-10-181-650/+403
| | | | | | | | | | This converts a large and somewhat arbitrary set of tests to use update_mir_test_checks. I ran the script on all of the tests I expect to need to modify for an upcoming mir syntax change and kept the ones that obviously didn't change the tests in ways that might make it harder to understand. llvm-svn: 316137
* [GISel]: Fix generation of illegal COPYs during CallLoweringAditya Nandakumar2017-10-091-26/+52
| | | | | | | | | | | We end up creating COPY's that are either truncating/extending and this should be illegal. https://reviews.llvm.org/D37640 Patch for X86 and ARM by igorb, rovka llvm-svn: 315240
* [ARM] GlobalISel: Make tests less strictDiana Picus2017-10-062-43/+12
| | | | | | | These are intended as integration tests, so they shouldn't be too specific about what they're checking. llvm-svn: 315083
* [ARM] GlobalISel: Select shiftsDiana Picus2017-10-061-0/+103
| | | | | | | | | Unfortunately TableGen doesn't handle this yet: Unable to deduce gMIR opcode to handle Src (which is a leaf). Just add some temporary hand-written code to generate the proper MOVsr. llvm-svn: 315071
* [ARM] GlobalISel: Map shift operands to GPRsDiana Picus2017-10-061-0/+82
| | | | llvm-svn: 315067
* [ARM] GlobalISel: Mark shifts as legal for s32Diana Picus2017-10-061-0/+79
| | | | | | | The new legalize combiner introduces shifts all over the place, so we should support them sooner rather than later. llvm-svn: 315064
* [ARM] GlobalISel: Support global variables for RWPIDiana Picus2017-09-053-12/+72
| | | | | | | | | In RWPI code, globals that are not read-only are accessed relative to the SB register (R9). This is achieved by explicitly generating an ADD instruction between SB and an offset that we either load from a constant pool or movw + movt into a register. llvm-svn: 312521
* [ARM] GlobalISel: Support ROPI global variablesDiana Picus2017-09-013-3/+198
| | | | | | | In the ROPI relocation model, read-only variables are accessed relative to the PC. We use the (MOV|LDRLIT)_ga_pcrel pseudoinstructions for this. llvm-svn: 312323
* [ARM] GlobalISel: More tests. NFC.Diana Picus2017-09-012-2/+116
| | | | | | | | Test constants as well in the PIC tests. These are also represented as G_GLOBAL_VALUE, and although they are treated just like other globals for PIC, they won't be for ROPI, so it's good to have this coverage. llvm-svn: 312319
* [GISel]: Add a clean up combiner during legalization.Aditya Nandakumar2017-08-301-16/+16
| | | | | | | | | | | Added a combiner which can clean up truncs/extends that are created in order to make the types work during legalization. Also moved the combineMerges to the LegalizeCombiner. https://reviews.llvm.org/D36880 llvm-svn: 312158
* [ARM] GlobalISel: Select globals in PIC modeDiana Picus2017-08-293-2/+121
| | | | | | | | | | | | | | Support the selection of G_GLOBAL_VALUE in the PIC relocation model. For simplicity we use the same pseudoinstructions for both Darwin and ELF: (MOV|LDRLIT)_ga_pcrel(_ldr). This is new for ELF, so it requires a small update to the ARM pseudo expansion pass to make sure it adds the correct constant pool modifier and add-current-address in the case of ELF. Differential Revision: https://reviews.llvm.org/D36507 llvm-svn: 311992
* [ARM] GlobalISel: Rename tests. NFC.Diana Picus2017-08-292-0/+0
| | | | | | | The checks are complicated enough as it is, there's no use cramming PIC in there as well... llvm-svn: 311989
* Fix ARMv4 supportJoerg Sonnenberger2017-08-281-2/+2
| | | | | | | | | | | | | | | | | | ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
* [ARM] GlobalISel: Select simple G_GLOBAL_VALUE instructionsDiana Picus2017-08-033-1/+159
| | | | | | | | | | | | | Add support in the instruction selector for G_GLOBAL_VALUE for ELF and MachO for the static relocation model. We don't handle Windows yet because that's Thumb-only, and we don't handle Thumb in general at the moment. Support for PIC, ROPI, RWPI and TLS will be added in subsequent commits. Differential Revision: https://reviews.llvm.org/D35883 llvm-svn: 309927
* [ARM] GlobalISel: Map G_GLOBAL_VALUE to GPRDiana Picus2017-07-261-0/+19
| | | | | | A G_GLOBAL_VALUE is basically a pointer, so it should live in the GPR. llvm-svn: 309101
* [ARM] GlobalISel: Mark G_GLOBAL_VALUE as legalDiana Picus2017-07-261-0/+26
| | | | llvm-svn: 309090
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