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path: root/llvm/test/CodeGen/ARM/2014-02-21-byval-reg-split-alignment.ll
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* ARM: simplify and extend byval handlingTim Northover2015-03-111-2/+3
| | | | | | | | | | | | | | | | | | | The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
* ARM: enable tail call optimisation on Thumb 2Saleem Abdulrasool2014-03-111-6/+6
| | | | | | | | | | | | Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. llvm-svn: 203575
* ARM: Correctly align arguments after a byval struct is passed on the stackOliver Stannard2014-03-051-0/+114
llvm-svn: 202985
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