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* AMDGPU/GlobalISel: Select G_SHLMatt Arsenault2019-07-163-0/+698
| | | | | | | | | | I think this manages to not break the DAG handling with the divergent predicates because the stadalone divergent patterns end up with a higher priority than the pattern on the instruction definition. The 16-bit versions don't work yet. llvm-svn: 366254
* [AMDGPU] Change register type for v32 vectorsStanislav Mekhanoshin2019-07-161-0/+29
| | | | | | | | | | When it is AReg_1024 this results in unnecessary copying into AGPRs of a 32 element vectors even though they are not intended for an mfma instruction. Differential Revision: https://reviews.llvm.org/D64815 llvm-svn: 366252
* AMDGPU/GlobalISel: Fix selection of private storesMatt Arsenault2019-07-161-0/+280
| | | | llvm-svn: 366249
* AMDGPU/GlobalISel: Select private loadsMatt Arsenault2019-07-161-0/+1158
| | | | llvm-svn: 366248
* AMDGPU/GlobalISel: Select flat storesMatt Arsenault2019-07-167-52/+1646
| | | | llvm-svn: 366246
* AMDGPU/GlobalISel: Select flat loadsMatt Arsenault2019-07-162-9/+3357
| | | | | | | | Now that the patterns use the new PatFrag address space support, the only blocker to importing most load patterns is the addressing mode complex patterns. llvm-svn: 366237
* [AMDGPU] Optimize atomic max/minJay Foad2019-07-161-0/+108
| | | | | | | | | | | | | | | | Summary: Extend the atomic optimizer to handle signed and unsigned max and min operations, as well as add and subtract. Reviewers: arsenm, sheredom, critson, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64328 llvm-svn: 366235
* [AMDGPU] Add the adjusted FP as a livein register.Michael Liao2019-07-161-0/+50
| | | | | | | | | | | | Reviewers: arsenm, rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64145 llvm-svn: 366223
* AMDGPU/GlobalISel: Fix test failures in release buildMatt Arsenault2019-07-1613-463/+400
| | | | | | | | | | | | Apparently the check for legal instructions during instruction select does not happen without an asserts build, so these would successfully select in release, and fail in debug. Make s16 and/or/xor legal. These can just be selected directly to the 32-bit operation, as is already done in SelectionDAG, so just make them legal. llvm-svn: 366210
* [AMDGPU] Enable merging m0 initializations.Austin Kerbow2019-07-151-7/+101
| | | | | | | | | | | | | | | | | | | | Summary: Enable hoisting and merging m0 defs that are initialized with the same immediate value. Fixes bug where removed instructions are not considered to interfere with other inits, and make sure to not hoist inits before block prologues. Reviewers: rampitec, arsenm Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64766 llvm-svn: 366135
* AMDGPU/GlobalISel: Allow scalar s1 and/or/xorMatt Arsenault2019-07-155-162/+1873
| | | | | | | | If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to whether the result is 0. If the inputs are SCC, these can be copied to a 32-bit SGPR to produce an SCC result. llvm-svn: 366125
* AMDGPU/GlobalISel: Select G_AND/G_OR/G_XORMatt Arsenault2019-07-153-24/+1762
| | | | llvm-svn: 366121
* AMDGPU/GlobalISel: Don't constrain source register of VCC copiesMatt Arsenault2019-07-151-4/+27
| | | | | | | | | | | | | This is a hack until I come up with a better way of dealing with the pseudo-register banks used for boolean values. If the use instruction constrains the register, the selector for the def instruction won't see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have been SCCRegBank or VCCRegBank in wave32. This is necessary to successfully select branches with and and/or/xor condition. llvm-svn: 366120
* AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copiesMatt Arsenault2019-07-151-3/+31
| | | | | | | | | The extra test change is correct, although how it arrives there is a bug that needs work. With wave32, the test for isVCC ambiguously reports true for an SCC or VCC source. A new allocatable pseudo register class for SCC may be necesssary. llvm-svn: 366119
* AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCCMatt Arsenault2019-07-151-0/+26
| | | | llvm-svn: 366118
* AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCCMatt Arsenault2019-07-151-9/+36
| | | | | | This was emitting a copy from a 32-bit register to a 64-bit. llvm-svn: 366117
* AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELTMatt Arsenault2019-07-151-3/+38
| | | | llvm-svn: 366116
* AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELTMatt Arsenault2019-07-151-102/+99
| | | | | | Turn the constant cases into G_EXTRACTs. llvm-svn: 366115
* AMDGPU/GlobalISel: Fix G_ICMP for wave32Matt Arsenault2019-07-151-6/+7
| | | | llvm-svn: 366114
* GlobalISel: Implement narrowScalar for vector extract/insert indexesMatt Arsenault2019-07-152-2/+63
| | | | llvm-svn: 366113
* AMDGPU/GlobalISel: Widen vector extractsMatt Arsenault2019-07-151-0/+366
| | | | llvm-svn: 366103
* AMDGPU/GlobalISel: Handle llvm.amdgcn.if.breakMatt Arsenault2019-07-152-0/+53
| | | | llvm-svn: 366102
* AMDGPU/GlobalISel: Select llvm.amdgcn.end.cfMatt Arsenault2019-07-152-0/+75
| | | | llvm-svn: 366099
* AMDGPU: Add 24-bit mul intrinsicsMatt Arsenault2019-07-156-11/+609
| | | | | | | | | | | Insert these during codegenprepare. This works around a DAG issue where generic combines eliminate the and asserting the high bits are zero, which then exposes an unknown read source to the mul combine. It doesn't worth the hassle of trying to insert an AssertZext or something to try to deal with it. llvm-svn: 366094
* AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTORMatt Arsenault2019-07-151-0/+152
| | | | llvm-svn: 366087
* AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORSMatt Arsenault2019-07-151-0/+69
| | | | llvm-svn: 366086
* [AMDGPU] fixed scheduler crash in gfx908Stanislav Mekhanoshin2019-07-151-0/+22
| | | | | | | | | For some reason scheduler can send down an SUnit without an instruction. Differential Revision: https://reviews.llvm.org/D64709 llvm-svn: 366074
* [AMDGPU] use v32f32 for 3 mfma intrinsicsStanislav Mekhanoshin2019-07-124-44/+48
| | | | | | | | | These should really use v32f32, but were defined as v32i32 due to the lack of the v32f32 type. Differential Revision: https://reviews.llvm.org/D64667 llvm-svn: 365972
* AMDGPU: Drop remnants of byval support for shadersMatt Arsenault2019-07-1213-38/+30
| | | | | | | | Before 2018, mesa used to use byval interchangably with inreg, which didn't really make sense. Fix tests still using it to avoid breaking in a future commit. llvm-svn: 365953
* [AMDGPU] Fix DPP combiner check for exec modificationJay Foad2019-07-126-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | Summary: r363675 changed the exec modification helper function, now called execMayBeModifiedBeforeUse, so that if no UseMI is specified it checks all instructions in the basic block, even beyond the last use. That meant that the DPP combiner no longer worked in any basic block that ended with a control flow instruction, and in particular it didn't work on code sequences generated by the atomic optimizer. Fix it by reinstating the old behaviour but in a new helper function execMayBeModifiedBeforeAnyUse, and limiting the number of instructions scanned. Reviewers: arsenm, vpykhtin Subscribers: kzhuravl, nemanjai, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kbarton, MaskRay, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64393 llvm-svn: 365910
* [AMDGPU] Restrict v_cndmask_b32 abs/neg modifiers to f32Jay Foad2019-07-121-0/+48
| | | | | | | | | | | | | | | | | | Summary: D64497 allowed abs/neg source modifiers on v_cndmask_b32 but it doesn't make any sense to apply them to f16 operands; they would interpret the bits of the value as an f32, giving nonsensical results. This patch restricts them to f32 operands. Reviewers: arsenm, hakzsam Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64636 llvm-svn: 365904
* [AMDGPU] Skip calculating callee saved registers for entry function.Michael Liao2019-07-111-0/+54
| | | | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64596 llvm-svn: 365846
* AMDGPU: s_waitcnt field should be treated as unsignedMatt Arsenault2019-07-111-0/+12
| | | | | | | Also make it an ImmLeaf, so it should work with global isel as well, which was part of the point of moving it in the first place. llvm-svn: 365842
* [AMDGPU] gfx908 agpr spillingStanislav Mekhanoshin2019-07-112-0/+396
| | | | | | Differential Revision: https://reviews.llvm.org/D64594 llvm-svn: 365833
* [AMDGPU] gfx908 hazard recognizerStanislav Mekhanoshin2019-07-111-0/+457
| | | | | | Differential Revision: https://reviews.llvm.org/D64593 llvm-svn: 365829
* [AMDGPU] gfx908 mfma supportStanislav Mekhanoshin2019-07-118-2/+1724
| | | | | | Differential Revision: https://reviews.llvm.org/D64584 llvm-svn: 365824
* [DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS supportSimon Pilgrim2019-07-112-2/+2
| | | | | | | | | | | | | | We already split extract_subvector(binop(insert_subvector(v,x),insert_subvector(w,y))) -> binop(x,y). This patch adds support for extract_subvector(binop(concat_vectors(),concat_vectors())) cases as well. In particular this means we don't have to wait for X86 lowering to convert concat_vectors to insert_subvector chains, which helps avoid some cases where demandedelts/combine calls occur too late to split large vector ops. The fast-isel-store.ll load folding regression is annoying but I don't think is that critical. Differential Revision: https://reviews.llvm.org/D63653 llvm-svn: 365785
* [AMDGPU] Regenerate idot tests. NFCI.Simon Pilgrim2019-07-113-56/+56
| | | | | | Reduces diff in D63281. llvm-svn: 365754
* [AMDGPU] gfx908 atomic fadd and atomic pk_faddStanislav Mekhanoshin2019-07-111-0/+72
| | | | | | Differential Revision: https://reviews.llvm.org/D64435 llvm-svn: 365717
* [AMDGPU] gfx908 dot instruction supportStanislav Mekhanoshin2019-07-112-0/+6
| | | | | | Differential Revision: https://reviews.llvm.org/D64431 llvm-svn: 365715
* GlobalISel: Legalization for G_FMINNUM/G_FMAXNUMMatt Arsenault2019-07-102-0/+1066
| | | | llvm-svn: 365658
* AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault2019-07-101-15/+9
| | | | llvm-svn: 365653
* [AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32Jay Foad2019-07-103-40/+20
| | | | | | | | | | | | | | | | | Summary: D59191 added support for these modifiers in the assembler and disassembler. This patch just teaches instruction selection that it can use them. Reviewers: arsenm, tstellar Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64497 llvm-svn: 365640
* AMDGPU/GlobalISel: Add support for wide loads >= 256-bitsTom Stellard2019-07-103-0/+548
| | | | | | | | | | | | | | | | | | Summary: This adds support for the most commonly used wide load types: <8xi32>, <16xi32>, <4xi64>, and <8xi64> Reviewers: arsenm Reviewed By: arsenm Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57399 llvm-svn: 365586
* GlobalISel: Implement lower for G_FCOPYSIGNMatt Arsenault2019-07-092-176/+671
| | | | | | | | | In SelectionDAG AMDGPU treated these as legal, but this was mostly because the bitcasts required for FP types were painful. Theoretically the bitpattern should eventually match to bfi, so don't bother trying to get the patterns to import. llvm-svn: 365583
* AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTORMatt Arsenault2019-07-0919-192/+600
| | | | llvm-svn: 365575
* GlobalISel: Combine unmerge of merge with intermediate castMatt Arsenault2019-07-091-0/+484
| | | | | | | This eliminates some illegal intermediate vectors when operations are scalarized. llvm-svn: 365566
* [AMDGPU] gfx908 register file changesStanislav Mekhanoshin2019-07-091-3/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D64438 llvm-svn: 365546
* [AMDGPU] gfx908 targetStanislav Mekhanoshin2019-07-093-0/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D64429 llvm-svn: 365525
* AMDGPU: Fix test failing since r365512Matt Arsenault2019-07-091-1/+1
| | | | llvm-svn: 365521
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