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* AMDGPU: Apply i16 add->sub pattern with zext to i32Matt Arsenault2020-01-071-1/+1
* [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtrJay Foad2019-12-171-20/+20
* [AMDGPU] Regenerate vector sub testsSimon Pilgrim2019-05-231-131/+525
* [AMDGPU] Remove useless check from test. NFC.Stanislav Mekhanoshin2018-09-251-1/+0
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-42/+44
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-191-2/+1
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-171-2/+2
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-5/+5
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-081-1/+1
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-2/+2
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-151-2/+3
* AMDGPU: Start selecting global instructionsMatt Arsenault2017-07-291-8/+8
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-8/+8
* [AMDGPU] Untangle SDWA pass from SIShrinkInstructionsStanislav Mekhanoshin2017-06-031-6/+6
* [AMDGPU] Allow SDWA in instructions with immediates and SGPRsStanislav Mekhanoshin2017-05-301-15/+15
* AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)Konstantin Zhuravlyov2017-04-211-1/+1
* [AMDGPU] Resubmit SDWA peephole: enable by defaultSam Kolton2017-04-061-3/+3
* Revert r299536. [AMDGPU] SDWA peephole: enable by default.Ivan Krasin2017-04-051-3/+3
* [AMDGPU] SDWA peephole: enable by defaultSam Kolton2017-04-051-3/+3
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-13/+13
* LiveRegMatrix: Fix some subreg interference checksMatthias Braun2017-03-021-5/+5
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-0/+278
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