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* Revert "AMDGPU: Try to commute sub of boolean ext"Tim Renouf2019-12-131-10/+15
| | | | | | | | | | | | | | | | | | | | This reverts commit 69fcfb7d3597e0cdb5554b4e672e9032b411b167. As shown in the test I attached to this commit, the change I reverted causes a problem with "zext(cc1) - zext(cc2)". It commuted the operands to the sub and used different logic to select the addc/subc instruction: sub zext (setcc), x => addcarry 0, x, setcc sub sext (setcc), x => subcarry 0, x, setcc ... but that is bogus. I believe it is not possible to fold those commuted patterns into any form of addcarry or subcarry. It may have worked as intended before "AMDGPU: Change boolean content type to 0 or 1" because the setcc was considered to be -1 rather than 1. Differential Revision: https://reviews.llvm.org/D70978 Change-Id: If2139421aa6c935cbd1d925af58fe4a4aa9e8f43
* AMDGPU: Change boolean content type to 0 or 1Matt Arsenault2019-11-151-8/+6
| | | | | | | | The usage of target boolean checks is overly inflexible, since sext and zext of a compare are equally cheap. The choice is arbitrary, but using 0/1 to some degree is the choice of lower resistance since that's what most targets use. This enables a few combines that don't bother to support ZeroOrNegativeOneBooleanContent.
* AMDGPU: Try to commute sub of boolean extMatt Arsenault2019-11-151-0/+43
| | | | Avoids another regression in a future patch.
* AMDGPU: Extend add x, (ext setcc) combine to subMatt Arsenault2019-11-131-0/+74
| | | | | | This is the same as the add case, but inverts the operation type. This avoids regressions in a future patch.
* [AMDGPU] fix commuted case of sub combineStanislav Mekhanoshin2019-02-211-0/+28
| | | | | | Differential Revision: https://reviews.llvm.org/D58481 llvm-svn: 354543
* [AMDGPU] A trivial fix for a buildbot failure caused by "commit ↵Farhana Aleen2018-05-021-0/+39
| | | | | | | 224a839fcbbead221f872cd32a1dd0c308d37299". Author: FarhanaAleen llvm-svn: 331383
* Revert "[AMDGPU] performAddCombine should run after DAG is legalized."Farhana Aleen2018-05-021-39/+0
| | | | | | This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494. llvm-svn: 331371
* [AMDGPU] performAddCombine should run after DAG is legalized.Farhana Aleen2018-05-021-0/+39
| | | | | | | | | | | | | | | | Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with illegal types. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D46337 llvm-svn: 331368
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-241-4/+4
| | | | | | | | | | V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when we try to commute V_SUBB_U32 in order to shrink it we do not then process V_SUBBREV_U32 and it stay VOP3. This is fixed. Differential Revision: https://reviews.llvm.org/D43699 llvm-svn: 326011
* [AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0Stanislav Mekhanoshin2017-06-271-0/+20
| | | | | | | | | | Also factored out function to check if a boolean is an already deserialized value which does not require v_cndmask_b32 to be loaded. Added binary logical operators to its check. Differential Revision: https://reviews.llvm.org/D34500 llvm-svn: 306439
* [AMDGPU] Add FP_CLASS to the add/setcc combineStanislav Mekhanoshin2017-06-211-0/+36
| | | | | | | | This is one of the nodes which also compile as v_cmp_*. Differential Revision: https://reviews.llvm.org/D34485 llvm-svn: 305970
* [AMDGPU] Combine add and adde, sub and subeStanislav Mekhanoshin2017-06-211-0/+80
| | | | | | | | | If one of the arguments of adde/sube is zero we can fold another add/sub into it. Differential Revision: https://reviews.llvm.org/D34374 llvm-svn: 305964
* [AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin2017-06-211-0/+43
This simplification allows to avoid generating v_cndmask_b32 to serialize condition code between compare and use. Differential Revision: https://reviews.llvm.org/D34300 llvm-svn: 305962
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