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* AMDGPU: Split flat offsets that don't fit in DAGMatt Arsenault2019-10-201-1/+4
| | | | | | | | | | We handle it this way for some other address spaces. Since r349196, SILoadStoreOptimizer has been trying to do this. This is after SIFoldOperands runs, which can change the addressing patterns. It's simpler to just split this earlier. llvm-svn: 375366
* CodeGenPrep: preserve inbounds attribute when sinking GEPs.Tim Northover2019-03-121-1/+1
| | | | | | | | | Targets can potentially emit more efficient code if they know address computations never overflow. For example ILP32 code on AArch64 (which only has 64-bit address computation) can ignore the possibility of overflow with this extra information. llvm-svn: 355926
* AMDGPU: Fix some outdated datalayouts in testsMatt Arsenault2018-09-131-1/+1
| | | | llvm-svn: 342131
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-36/+36
| | | | | | Differential Revision: https://reviews.llvm.org/D43170 llvm-svn: 325030
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-021-17/+17
| | | | | | | | This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
* AMDGPU: Teach isLegalAddressingMode about global_* instructionsMatt Arsenault2017-07-291-10/+75
| | | | | | | | Also refine the flat check to respect flat-for-global feature, and constant fallback should check global handling, not specifically MUBUF. llvm-svn: 309471
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-041-3/+3
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307097
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-041-3/+3
| | | | | | | | | It broke a testcase. Failing Tests (1): LLVM :: CodeGen/AMDGPU/alignbit-pat.ll llvm-svn: 307054
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-031-3/+3
| | | | | | Differential revision: https://reviews.llvm.org/D34407 llvm-svn: 307026
* Turn on -addr-sink-using-gep by default.Eli Friedman2017-04-061-22/+21
| | | | | | | | | The new codepath has been in the tree for years, and there isn't any reason to use two codepaths here. Differential Revision: https://reviews.llvm.org/D30596 llvm-svn: 299723
* AMDGPU: Add all atomicrmw fields to atomic.inc/decMatt Arsenault2017-03-301-6/+6
| | | | | | Add scope, order, isVolatile llvm-svn: 299122
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-22/+22
| | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
* AMDGPU: Allow sinking of addressing modes for atomic_inc/decMatt Arsenault2017-03-151-0/+55
| | | | llvm-svn: 297913
* CodeGenPrepare: Sink addressing modes for atomicsMatt Arsenault2017-03-151-1/+82
| | | | llvm-svn: 297903
* AMDGPU: Always allocate emergency stack slot at offset 0Matt Arsenault2017-02-221-2/+43
| | | | | | | | | This allows us to ensure that 0 is never a valid pointer to a user object, and ensures that the offset is always legal without needing a register to access it. This comes at the cost of usable offsets and wasted stack space. llvm-svn: 295877
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-2/+2
| | | | | | | | | | | This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
* Reapply "AMDGPU: Don't use offen if it is 0"Matt Arsenault2016-10-261-2/+2
| | | | | | This reverts r283003 llvm-svn: 285203
* Revert "AMDGPU: Don't use offen if it is 0"Mehdi Amini2016-10-011-2/+2
| | | | | | | This reverts commit r282999. Tests are not passing: http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules/builds/20038 llvm-svn: 283003
* AMDGPU: Don't use offen if it is 0Matt Arsenault2016-10-011-2/+2
| | | | | | This removes many re-initializations of a base register to 0. llvm-svn: 282999
* AMDGPU: Fix missing test for addressing mode with odd offsetsMatt Arsenault2016-08-131-5/+31
| | | | | | Add test if the constant offset looks unaligned. llvm-svn: 278589
* AMDGPU: Merge / reorganize testsMatt Arsenault2016-07-091-0/+28
| | | | llvm-svn: 274972
* AMDGPU: Move subtarget feature checks into passesMatt Arsenault2016-06-271-3/+3
| | | | llvm-svn: 273937
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-28/+46
| | | | | | | | | | Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
* AMDGPU: Set flat_scratch from flat_scratch_init regMatt Arsenault2016-02-121-2/+0
| | | | | | | | | | | | | | This was hardcoded to the static private size, but this would be missing the offset and additional size for someday when we have dynamic sizing. Also stops always initializing flat_scratch even when unused. In the future we should stop emitting this unless flat instructions are used to access private memory. For example this will initialize it almost always on VI because flat is used for global access. llvm-svn: 260658
* AMDGPU: Remove some old intrinsic uses from testsMatt Arsenault2016-02-111-2/+0
| | | | llvm-svn: 260493
* AMDGPU/SI: Fold operands through REG_SEQUENCE instructionsTom Stellard2015-09-091-4/+2
| | | | | | | | | | | | | | Summary: This helps mostly when we use add instructions for address calculations that contain immediates. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12256 llvm-svn: 247157
* AMDGPU: Assume SMRD access for constant address spaceMatt Arsenault2015-08-071-32/+224
| | | | | | | Since r243294 these are selected to SMRD and moved later if required. llvm-svn: 244354
* AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory opsTom Stellard2015-07-201-5/+11
| | | | | | | | | | | | | | Summary: The MUBUF addr64 bit has been removed on VI, so we must use FLAT instructions when the pointer is stored in VGPRs. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11067 llvm-svn: 242673
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+242
llvm-svn: 239657
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