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* GlobalISel: Implement fewerElementsVector for shiftsMatt Arsenault2019-02-073-108/+1263
| | | | | | | | | Introduce a new function which handles instructions with multiple type indices, but have the same number of vector elements. Also legalize v2s16 shifts when applicable. llvm-svn: 353432
* GlobalISel: Consolidate load/store legalizationMatt Arsenault2019-02-052-51/+88
| | | | | | | | | | The fewerElementsVectors implementation for load/stores handles the scalar reduction case just as well, so drop the redundant code in narrowScalar. This also introduces support for narrowing irregular size breakdowns for scalars. llvm-svn: 353125
* GlobalISel: Implement narrowScalar for selectMatt Arsenault2019-02-051-2/+143
| | | | | | | | | | Don't handle vector conditions. I think this can be merged in the future with fewerElementsVectorSelect, although this becomes slightly tricky with a vector condition. llvm-svn: 353122
* GlobalISel: Combine g_extract with g_merge_valuesMatt Arsenault2019-02-041-0/+470
| | | | | | | | | | | | | | Try to use the underlying source registers. This enables legalization in more cases where some irregular operations are widened and others narrowed. This seems to make the test_combines_2 AArch64 test worse, since the MERGE_VALUES has multiple uses. Since this should be required for legalization, a hasOneUse check is probably inappropriate (or maybe should only be used if the merge is legal?). llvm-svn: 353121
* GlobalISel: Enforce operand types for constantsMatt Arsenault2019-02-0413-46/+47
| | | | | | | | A number of of tests were using imm operands, not cimm. Since CSE relies on the exact ConstantInt* pointer used, and implicit conversions are generally evil, also enforce the bitsize of the types. llvm-svn: 353113
* GlobalISel: Fix not calling observer when legalizing bitcount opsMatt Arsenault2019-02-045-20/+41
| | | | | | This was hiding bugs from never legalizing the source type. llvm-svn: 353102
* AMDGPU/GlobalISel: Legalize select for v4s16Matt Arsenault2019-02-041-1/+206
| | | | | | | Also add some more select tests to help show future legalization changes. llvm-svn: 353045
* GlobalISel: Implement widenScalar for G_UNMERGE_VALUESMatt Arsenault2019-02-031-1/+232
| | | | | | | | | For the scalar case only. Also move the similar G_MERGE_VALUES handling to a separate function and cleanup to make them look more similar. llvm-svn: 352979
* GlobalISel: Implement widenScalar for G_EXTRACT vector sourcesMatt Arsenault2019-02-021-0/+132
| | | | | | Handle the basic element extract case. llvm-svn: 352978
* AMDGPU/GlobalISel: Legalize icmp for pointer typesMatt Arsenault2019-02-021-0/+175
| | | | llvm-svn: 352976
* AMDGPU/GlobalISel: Legalize constant for pointer typesMatt Arsenault2019-02-021-0/+84
| | | | llvm-svn: 352975
* AMDGPU/GlobalISel: Legalize select for pointer typesMatt Arsenault2019-02-021-76/+514
| | | | llvm-svn: 352974
* GlobalISel: Legalization for inttoptr/ptrtointMatt Arsenault2019-02-022-28/+323
| | | | llvm-svn: 352973
* GlobalISel: Handle odd splits in fewerElementsVector for load/storeMatt Arsenault2019-01-312-123/+248
| | | | llvm-svn: 352720
* GlobalISel: Implement narrowScalar for bswapMatt Arsenault2019-01-311-0/+125
| | | | llvm-svn: 352719
* GlobalISel: Allow bitcount ops to have different result typeMatt Arsenault2019-01-315-0/+440
| | | | | | For AMDGPU the result is always 32-bit for 64-bit inputs. llvm-svn: 352717
* GlobalISel: Implement fewerElementsVector for selectMatt Arsenault2019-01-301-0/+209
| | | | llvm-svn: 352601
* AMDGPU/GlobalISel: Fix clamping shifts with 16-bit instsMatt Arsenault2019-01-303-0/+126
| | | | llvm-svn: 352599
* GlobalISel: Support narrowScalar for uneven loadsMatt Arsenault2019-01-301-1/+120
| | | | llvm-svn: 352594
* GlobalISel: Handle some odd splits in fewerElementsVectorMatt Arsenault2019-01-301-3/+75
| | | | | | Also add some quick hacks to AMDGPU legality for the tests. llvm-svn: 352591
* GlobalISel: Handle more cases for widenScalar for G_STOREMatt Arsenault2019-01-301-0/+99
| | | | llvm-svn: 352585
* GlobalISel: Verify pointer castsMatt Arsenault2019-01-291-8/+8
| | | | | | | Not sure if the old AArch64 tests should be just deleted or not. llvm-svn: 352562
* GlobalISel: Partially implement widenScalar for MERGE_VALUESMatt Arsenault2019-01-291-0/+156
| | | | llvm-svn: 352560
* GlobalISel: Fix narrowScalar for load/store with different mem sizeMatt Arsenault2019-01-292-0/+132
| | | | | | | | | | This was ignoring the memory size, and producing multiple loads/stores if the operand size was different from the memory size. I assume this is the intent of not having an explicit G_ANYEXTLOAD (although I think that would probably be better). llvm-svn: 352523
* GlobalISel: Don't reduce elements for atomic load/storeMatt Arsenault2019-01-271-0/+46
| | | | | | | This is invalid for the same reason as in the narrowScalar handling for load. llvm-svn: 352334
* GlobalISel: Verify load/store has a pointer inputMatt Arsenault2019-01-2713-38/+38
| | | | | | | I expected this to be automatically verified, but it seems nothing uses that the type index was declared as a "ptype" llvm-svn: 352319
* GlobalISel: Implement narrowScalar for mulMatt Arsenault2019-01-271-0/+26
| | | | llvm-svn: 352300
* GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_roundMatt Arsenault2019-01-272-8/+92
| | | | llvm-svn: 352298
* AMDGPU/GlobalISel: Legalize more bit opsMatt Arsenault2019-01-263-24/+567
| | | | llvm-svn: 352295
* AMDGPU/GlobalISel: Widen small uaddo/usuboMatt Arsenault2019-01-262-0/+194
| | | | llvm-svn: 352294
* AMDGPU/GlobalISel: Scalarize add/subMatt Arsenault2019-01-252-2/+64
| | | | llvm-svn: 352167
* GlobalISel: fewerElementsVector for more cast typesMatt Arsenault2019-01-254-0/+151
| | | | llvm-svn: 352166
* GlobalISel: fewerElementsVector for a few more trivial opsMatt Arsenault2019-01-256-0/+332
| | | | llvm-svn: 352165
* AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mulMatt Arsenault2019-01-255-2/+238
| | | | llvm-svn: 352162
* GlobalISel: Support fewerElementsVector for icmp/fcmpMatt Arsenault2019-01-252-13/+285
| | | | | | Also legalize 64-bit compares for AMDGPU llvm-svn: 352157
* GlobalISel: Implement fewerElementsVector for extensionsMatt Arsenault2019-01-255-7/+483
| | | | llvm-svn: 352155
* [GISel]: Change how CSE is enabled by default for each passAditya Nandakumar2019-01-241-1/+1
| | | | | | | | | | | | | | | https://reviews.llvm.org/D57178 Now add a hook in TargetPassConfig to query if CSE needs to be enabled. By default this hook returns false only for O0 opt level but this can be overridden by the target. As a consequence of the default of enabled for non O0, a few tests needed to be updated to not use CSE (by passing in -O0) to the run line. reviewed by: arsenm llvm-svn: 352126
* RegBankSelect: Support some more complex part mappingsMatt Arsenault2019-01-241-0/+386
| | | | llvm-svn: 352123
* AMDGPU/GlobalISel: Start selectively legalizing 16-bit operationsMatt Arsenault2019-01-223-51/+603
| | | | | | | | It might be a bit nicer to use the fancy .legalIf and co. predicates, but this was requiring more boilerplate and disables the coverage assertions. llvm-svn: 351886
* AMDGPU/GlobalISel: Handle legality/regbanks for 32/64-bit shiftsMatt Arsenault2019-01-227-16/+374
| | | | llvm-svn: 351884
* GlobalISel: Implement widen for extract_vector_elt elt typeMatt Arsenault2019-01-221-11/+92
| | | | llvm-svn: 351871
* GlobalISel: Implement fewerElementsVector for basic FP opsMatt Arsenault2019-01-226-0/+2146
| | | | llvm-svn: 351866
* GlobalISel: Support narrowing zextload/sextloadMatt Arsenault2019-01-228-0/+747
| | | | llvm-svn: 351856
* GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANTMatt Arsenault2019-01-221-25/+25
| | | | llvm-svn: 351853
* AMDGPU/GlobalISel: Legalize more fp<->int conversionsMatt Arsenault2019-01-224-7/+90
| | | | llvm-svn: 351767
* AMDGPU: Legalize more bitcastsMatt Arsenault2019-01-201-5/+169
| | | | llvm-svn: 351700
* AMDGPU/GlobalISel: Really legalize exts from i1Matt Arsenault2019-01-202-20/+42
| | | | | | | | There is a combine that was hiding these tests not actually testing what they should be, although they were producing the expected end result. llvm-svn: 351698
* GlobalISel: Implement widenScalar for basic FP opsMatt Arsenault2019-01-206-57/+490
| | | | llvm-svn: 351696
* AMDGPU/GlobalISel: Legalize f32->f16 fptruncMatt Arsenault2019-01-201-2/+19
| | | | llvm-svn: 351695
* AMDGPU/GlobalISel: Fix some crashs in g_unmerge_values/g_merge_valuesMatt Arsenault2019-01-202-4/+77
| | | | | | | | | | | This was crashing in the predicate function assuming the value is a vector. Copy more of what AArch64 uses. This probably needs more refinement later, but I don't exactly understand what it means in some cases, particularly since any legalization for these seems to be missing. llvm-svn: 351693
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