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* Revert "[GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELT"Jessica Paquette2019-03-052-197/+0
| | | | | | | | | | | This broke test-suite::aarch64_neon_intrinsics.test Reverting while I look into it. Example failure: http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/17740 llvm-svn: 355408
* [GlobalISel][AArch64] Add selection support for G_EXTRACT_VECTOR_ELTJessica Paquette2019-03-042-0/+197
| | | | | | | | | | | | | This adds instruction selection support for G_EXTRACT_VECTOR_ELT for cases where the index is defined by a G_CONSTANT. It also factos out the lane copy opcode selection part into its own function, `getLaneCopyOpcode`. This is used by both `selectUnmergeValues` and `selectExtractElt`. Differential Revision: https://reviews.llvm.org/D58469 llvm-svn: 355344
* [GlobalISel][AArch64] Legalize vector G_SELECTJessica Paquette2019-03-041-0/+69
| | | | | | | | Just scalarize it, and add a test showing it works. Differential Revision: https://reviews.llvm.org/D58747 llvm-svn: 355339
* Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector ↵Amara Emerson2019-03-041-25/+49
| | | | | | | | | | | | shuffle using TBL1." The code to materialize a mask from a constant pool load tried to use a 128 bit LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted in a link failure in the NEON tests in the test suite since the LDR address was unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is 64 bit, before converting back to a 128 bit register for the TBL. llvm-svn: 355326
* [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast ↵Craig Topper2019-03-041-2/+1
| | | | | | | | | | (build_vector constants)) between legalize types and legalize dag. This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality Differential Revision: https://reviews.llvm.org/D58884 llvm-svn: 355324
* [Codegen] fix typos in test caseXing GUO2019-03-021-3/+3
| | | | llvm-svn: 355264
* [AArch64] [Windows] Don't skip constructing UnwindHelp.Eli Friedman2019-02-283-6/+46
| | | | | | | | | | | | | In certain cases, the first non-frame-setup instruction in a function is a branch. For example, it could be a cbz on an argument. Make sure we correctly allocate the UnwindHelp, and find an appropriate register to use to initialize it. Fixes https://bugs.llvm.org/show_bug.cgi?id=40184 Differential Revision: https://reviews.llvm.org/D58752 llvm-svn: 355136
* [AArch64] Improve FP16 vector convert from short instructions.Abderrazek Zaafrani2019-02-282-28/+33
| | | | | | https://reviews.llvm.org/D58563 llvm-svn: 355134
* Revert "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."Amara Emerson2019-02-281-47/+25
| | | | | | Seems to break some neon intrinsics tests. llvm-svn: 355115
* [AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1.Amara Emerson2019-02-281-25/+47
| | | | | | | | | This extends the existing support for shufflevector to handle cases like <2 x float>, which we can implement by concating the vectors and using a TBL1. Differential Revision: https://reviews.llvm.org/D58684 llvm-svn: 355104
* [AArch64] Generate FP16 vector compare instructions.Abderrazek Zaafrani2019-02-282-238/+36
| | | | | | https://reviews.llvm.org/D58561 llvm-svn: 355050
* [AArch64] Add arithmetic zext bswap tests.Simon Pilgrim2019-02-261-0/+30
| | | | | | As requested on D58017. llvm-svn: 354872
* [AArch64] Add 'free' zext bswap tests.Simon Pilgrim2019-02-261-0/+28
| | | | | | As requested on D58017. llvm-svn: 354869
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+2
| | | | | | | | - Add LLVM backend support for Cortex-A76 and Cortex-A76AE - Documentation can be found at https://developer.arm.com/products/processors/cortex-a/cortex-a76 llvm-svn: 354788
* Fixed typos in tests: s/CHEKC/CHECK/Dmitri Gribenko2019-02-251-1/+1
| | | | | | | | | | | | Reviewers: ilya-biryukov Subscribers: nemanjai, javed.absar, jsji, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D58611 llvm-svn: 354785
* Fixed typos in tests: s/CEHCK/CHECK/Dmitri Gribenko2019-02-251-3/+3
| | | | | | | | | | | | Reviewers: ilya-biryukov Subscribers: sanjoy, sdardis, javed.absar, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58608 llvm-svn: 354781
* [LegalizeTypes][AArch64][X86] Make type legalization of vector ↵Craig Topper2019-02-242-59/+44
| | | | | | | | | | | | | | | | | | | | | (S/U)ADD/SUB/MULO follow getSetCCResultType for the overflow bits. Make UnrollVectorOverflowOp properly convert from scalar boolean contents to vector boolean contents Summary: When promoting the over flow vector for these ops we should use the target's desired setcc result type. This way a v8i32 result type will use a v8i32 overflow vector instead of a v8i16 overflow vector. A v8i16 overflow vector will cause LegalizeDAG/LegalizeVectorOps to have to use v8i32 and truncate to v8i16 in its expansion. By doing this in type legalization instead, we get the truncate into the DAG earlier and give DAG combine more of a chance to optimize it. We also have to fix unrolling to use the scalar setcc result type for the scalarized operation, and convert it to the required vector element type after the scalar operation. We have to observe the vector boolean contents when doing this conversion. The previous code was just taking the scalar result and putting it in the vector. But for X86 and AArch64 that would have only put a the boolean value in bit 0 of the element and left all other bits in the element 0. We need to ensure all bits in the element are the same. I'm using a select with constants here because that's what setcc unrolling in LegalizeVectorOps used. Reviewers: spatel, RKSimon, nikic Reviewed By: nikic Subscribers: javed.absar, kristof.beyls, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58567 llvm-svn: 354753
* [CGP] add special-cases to form unsigned add with overflow (PR40486)Sanjay Patel2019-02-241-16/+10
| | | | | | | | | | | | | | | | | | | | There's likely a missed IR canonicalization for at least 1 of these patterns. Otherwise, we wouldn't have needed the pattern-matching enhancement in D57516. Note that -- unlike usubo added with D57789 -- the TLI hook for this transform defaults to 'on'. So if there's any perf fallout from this, targets should look at how they're lowering the uaddo node in SDAG and/or override that hook. The x86 diffs suggest that there's some missing pattern-matching for forming inc/dec. This should fix the remaining known problems in: https://bugs.llvm.org/show_bug.cgi?id=40486 https://bugs.llvm.org/show_bug.cgi?id=31754 llvm-svn: 354746
* [CGP] add tests for uaddo increment/decrement; NFCSanjay Patel2019-02-221-0/+71
| | | | llvm-svn: 354699
* [DAGCombine] Fold overlapping constant storesNirav Dave2019-02-221-2/+2
| | | | | | | | | | | | | | | Fold a smaller constant store into larger constant stores immediately preceeding it. Reviewers: rnk, courbet Subscribers: javed.absar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58468 llvm-svn: 354676
* Re-land "[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR""Amara Emerson2019-02-213-1/+206
| | | | | | | Thanks to Richard Trieu for pointing out that the failures were due to a use-after-free of an ArrayRef. llvm-svn: 354616
* Add skipFunction to PostRA machine sinking pass.Xin Tong2019-02-211-0/+40
| | | | | | | | | | | | | | Summary: Add skipFunction to PostRA machine sinking pass. Reviewers: junbuml Subscribers: arsenm, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57847 llvm-svn: 354541
* Revert "[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR"Amara Emerson2019-02-213-206/+1
| | | | | | This reverts r354521 because it broke the bots, but passes on Darwin somehow. llvm-svn: 354532
* [GlobalISel] Add -O0 to some tests to see if it fixes them. I can't ↵Amara Emerson2019-02-202-2/+2
| | | | | | | | | | reproduce the failures locally, and greendragon also passes, but some other bots fail for reasons I don't understand. The only difference I can see between these tests is it's missing an -O0 If this doesn't work I'll revert and continue investigating. llvm-svn: 354529
* [AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTORAmara Emerson2019-02-203-1/+206
| | | | | | | | | | | | | | This change makes some basic type combinations for G_SHUFFLE_VECTOR legal, and implements them with a very pessimistic TBL2 instruction in the selector. For TBL2, support is also needed to generate constant pool entries and load from them in order to materialize the mask register. Currently supports <2 x s64> and <4 x s32> result types. Differential Revision: https://reviews.llvm.org/D58466 llvm-svn: 354521
* [DAGCombine] Generalize Dead Store to overlapping stores.Nirav Dave2019-02-201-3/+3
| | | | | | | | | | | | | | | | | | Summary: Remove stores that are immediately overwritten by larger stores. Reviewers: courbet, rnk Reviewed By: rnk Subscribers: javed.absar, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58467 llvm-svn: 354518
* [SDAG] Support vector UMULO/SMULONikita Popov2019-02-201-0/+401
| | | | | | | | | | | | | | | Second part of https://bugs.llvm.org/show_bug.cgi?id=40442. This adds an extra UnrollVectorOverflowOp() method to SDAG, because the general UnrollOverflowOp() method can't deal with multiple results. Additionally we need to expand UMULO/SMULO during vector op legalization, as it may result in unrolling, which may need additional type legalization. Differential Revision: https://reviews.llvm.org/D57997 llvm-svn: 354513
* AArch64/test: Add check for function name to machine-outliner-bad-adrp.mirTom Stellard2019-02-201-0/+1
| | | | | | | | | | | | | | | | | | | Summary: This test was failing in one of our setups because the generated ModuleID had the full path of the test file and that path contained the string BL. Reviewers: t.p.northover, jpaquette, paquette Reviewed By: paquette Subscribers: javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58217 llvm-svn: 354497
* [GlobalISel][AArch64] Legalize + select some llvm.ctlz.* intrinsicsJessica Paquette2019-02-184-1/+228
| | | | | | | | | | | | Legalize/select llvm.ctlz.* Add select-ctlz to show that we actually select them. Update arm64-clrsb.ll and arm64-vclz.ll to show that we perform valid transformations in optimized builds, and document where GISel can improve. Differential Revision: https://reviews.llvm.org/D58155 llvm-svn: 354299
* Try to organize MachineVerifier testsMatt Arsenault2019-02-152-54/+0
| | | | | | | | | | The Verifier is separate from the MachineVerifier, so move it to a different directory. Some other verifier tests were scattered in target codegen tests as well (although I'm sure I missed some). Work towards using a more consistent naming scheme to make it clearer where the gaps still are for generic instructions. llvm-svn: 354138
* Relax test to check for a valid number instead of a specific numberDouglas Yung2019-02-141-1/+1
| | | | | | to be like every other check in this test. llvm-svn: 354007
* [AArch64] Support reserving arbitrary general purpose registersPetr Hosek2019-02-132-15/+138
| | | | | | | | | | | | This is a follow up to D48580 and D48581 which allows reserving arbitrary general purpose registers with the exception of registers with special purpose (X8, X16-X18, X29, X30) and registers used by LLVM (X0, X19). This change also generalizes some of the existing logic to rely entirely on values generated from tablegen. Differential Revision: https://reviews.llvm.org/D56305 llvm-svn: 353957
* [AArch64] Expand v8i8 cttz (PR39729)Nikita Popov2019-02-121-0/+124
| | | | | | | | | | | Fix for https://bugs.llvm.org/show_bug.cgi?id=39729. Rather than adding just a case for v8i8 I'm setting cttz to expand for all vector types. Differential Revision: https://reviews.llvm.org/D58008 llvm-svn: 353872
* [GlobalISel][AArch64] Select llvm.bswap* for non-vector typesJessica Paquette2019-02-122-1/+18
| | | | | | | | | | | | | | | | This teaches the IRTranslator to emit G_BSWAP when it runs into Intrinsic::bswap. This allows us to select G_BSWAP for non-vector types in AArch64. Add a select-bswap.mir test, and add global isel checks to a couple existing tests in test/CodeGen/AArch64. This doesn't handle every bswap case, since some of these rely on known bits stuff. This just lets us handle the naive case. Differential Revision: https://reviews.llvm.org/D58081 llvm-svn: 353861
* [globalisel] Correct string emitted by GISelChangeObserver::erasingInstr()Daniel Sanders2019-02-111-2/+2
| | | | | | The API indicates that the MI is about to be erased rather than it has been erased. llvm-svn: 353746
* [AArch64][GlobalISel] Add isel support for a couple vector exts/truncsJessica Paquette2019-02-112-1/+107
| | | | | | | | | | | | | | Add support for - v4s16 <-> v4s32 - v2s64 <-> v2s32 And update tests that use them to show that we generate the correct instructions. Differential Revision: https://reviews.llvm.org/D57832 llvm-svn: 353732
* [GlobalISel][AArch64] NFC: Remove unnecessary IR from select-fp-casts.mirJessica Paquette2019-02-111-32/+0
| | | | | | | The IR section in this test doesn't do anything, so there's no point in it being there. Since it's redundant, just remove it. llvm-svn: 353731
* [GlobalISel][AArch64] Select G_FFLOORJessica Paquette2019-02-113-0/+171
| | | | | | | | | | | This teaches the legalizer about G_FFLOOR, and lets us select G_FFLOOR in AArch64. It updates the existing floating point tests, and adds a select-floor.mir test. Differential Revision: https://reviews.llvm.org/D57486 llvm-svn: 353722
* Recommit "[GlobalISel] Add IRTranslator support for G_FFLOOR"Jessica Paquette2019-02-111-0/+8
| | | | | | | | | After the changes introduced in r353586, this instruction doesn't cause any issues for any backend. Original review: https://reviews.llvm.org/D57485 llvm-svn: 353720
* GlobalISel: Add G_FCANONICALIZE instructionMatt Arsenault2019-02-112-0/+13
| | | | llvm-svn: 353719
* [GlobalISel] Regex the opcodes in unit test to fix non-deterministic orderingMandeep Singh Grang2019-02-101-7/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D57988 llvm-svn: 353652
* [AArch64] Regenerate bswap testsSimon Pilgrim2019-02-101-59/+131
| | | | llvm-svn: 353648
* Recommit "[GlobalISel] Introduce a generic floating point floor opcode, ↵Jessica Paquette2019-02-091-1/+4
| | | | | | | | | G_FFLOOR"" After r353586, we won't fail on the AMDGPU floor pattern that was killing the importer before. llvm-svn: 353589
* Re-apply r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-081-0/+35
| | | | | | | | CSEMIRBuilder" With a fix after r353563 that adds some more opcodes. llvm-svn: 353579
* Revert r353553 "[GISel][NFC]: Add missing call to record CSE hits in the ↵Francis Visoiu Mistrih2019-02-081-35/+0
| | | | | | | | | | | | CSEMIRBuilder" This reverts commit r353553. This breaks CodeGen/AArch64/GlobalISel/legalize-ext-csedebug-output.mir: http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-incremental/57963/console llvm-svn: 353575
* [DAGCombine] Optimize pow(X, 0.75) to sqrt(X) * sqrt(sqrt(X))Nemanja Ivanovic2019-02-081-0/+48
| | | | | | | | | | | | The sqrt case is faster and we already do this for the case where the exponent is 0.25. This adds the 0.75 case which is also not sensitive to signed zeros. Patch by Whitney Tsang (Whitney) Differential revision: https://reviews.llvm.org/D57434 llvm-svn: 353557
* [GISel][NFC]: Add missing call to record CSE hits in the CSEMIRBuilderAditya Nandakumar2019-02-081-0/+35
| | | | | | | | | | https://reviews.llvm.org/D57932 Add some logging + tests to make sure CSEInfo prints debug output. reviewed by: arsenm llvm-svn: 353553
* [AArch64] Fix condition for "high-vector" DUP optimizations.Eli Friedman2019-02-083-13/+252
| | | | | | | | | | | | | | | | AArch64 NEON has a bunch of instructions with a "2" suffix that extract the top half of the source vectors, instead of the bottom half. We have some DAGCombines to try to take advantage of that. However, they assumed that any EXTRACT_VECTOR was extracting the high half of the vector in question. This issue has apparently existed since the AArch64 backend was merged. Fixes https://bugs.llvm.org/show_bug.cgi?id=40632 . Differential Revision: https://reviews.llvm.org/D57862 llvm-svn: 353486
* [CodeGen] Handle vector UADDO, SADDO, USUBO, SSUBONikita Popov2019-02-071-0/+319
| | | | | | | | | | | | | | | This is part of https://bugs.llvm.org/show_bug.cgi?id=40442. Vector legalization is implemented for the add/sub overflow opcodes. UMULO/SMULO are also handled as far as legalization is concerned, but they don't support vector expansion yet (so no tests for them). The vector result widening implementation is suboptimal, because it could result in a legalization loop. Differential Revision: https://reviews.llvm.org/D57639 llvm-svn: 353464
* GlobalISel: Implement narrowScalar for shift main typeMatt Arsenault2019-02-073-21/+127
| | | | | | | | | | | | | | | This is pretty much directly ported from SelectionDAG. Doesn't include the shift by non-constant but known bits version, since there isn't a globalisel version of computeKnownBits yet. This shows a disadvantage of targets not specifically which type should be used for the shift amount. If type 0 is legalized before type 1, the operations on the shift amount type use the wider type (which are also less likely to legalize). This can be avoided by targets specifying legalization actions on type 1 earlier than for type 0. llvm-svn: 353455
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