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* verify-uselistorder: Change the default -num-shuffles=5Duncan P. N. Exon Smith2014-07-311-1/+1
| | | | | | | Change the default for `-num-shuffles` to 5 and better document the algorithm in the header docs of `verify-uselistorder`. llvm-svn: 214419
* Rename llvm-uselistorder => verify-uselistorderDuncan P. N. Exon Smith2014-07-301-1/+1
| | | | llvm-svn: 214318
* Bitcode: Correctly compare a Use against itselfDuncan P. N. Exon Smith2014-07-291-0/+1
| | | | | | | | | | | | | | | Fix the sort of expected order in the reader to correctly return `false` when comparing a `Use` against itself. This was caught by test/Bitcode/binaryIntInstructions.3.2.ll, so I'm adding a `RUN` line using `llvm-uselistorder` for every test in `test/Bitcode` that passes. A few tests still fail, so I'll investigate those next. This is part of PR5680. llvm-svn: 214157
* Fix line-endings, NFCDuncan P. N. Exon Smith2014-07-291-328/+328
| | | | | | | A follow-up commit is adding a RUN line to each of these tests, so fix the line endings first. This is a whitespace-only change. llvm-svn: 214156
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-131-20/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-111-40/+40
| | | | | | | | | | | | | | | The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
* Ensure bitcode encoding of instructions and their operands stays stable.Michael Kuperstein2014-03-021-0/+308
This includes instructions that relate to memory access (load/store/GEP), comparison instructions and calls. Work was done by lama.saba@intel.com. llvm-svn: 202647
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