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ISD::MULHS/ISD::MULHU lowering of vXi8 types means we expand these in TargetLowering BuildSDIV/BuildUDIV.
llvm-svn: 345175
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Non-uniform division/remainder handling was added back at D49248/D50765 - so share the 'mul+sub' costs that already exist for uniform cases.
llvm-svn: 345164
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difference in lowering.
llvm-svn: 345048
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llvm-svn: 345045
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Just f64/i64 tests initially to demonstrate PR39368
llvm-svn: 344857
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llvm-svn: 344846
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Summary: This was inheriting the cost from the AVX table, but should be legal under AVX512.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D51267
llvm-svn: 340708
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Add ConstantInt analysis to getOperandInfo so we get more realistic div/rem expansion costs comparable to the vector costs.
llvm-svn: 336827
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We penalize general SDIV/UDIV costs but don't do the same for SREM/UREM.
This patch makes general vector SREM/UREM x20 as costly as scalar, the same approach as we do for SDIV/UDIV. The patch also extends the existing SDIV/UDIV constant costs for SREM/UREM - at the moment this means the additional cost of a MUL+SUB (see D48975).
Differential Revision: https://reviews.llvm.org/D48980
llvm-svn: 336486
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Normally InstCombine would have simplified these to SRL/AND instructions but we may still see these during SLP vectorization etc.
llvm-svn: 336371
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Add cost tests for fp ceil, floor, nearbyint, rint and trunc.
llvm-svn: 336122
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These were being over cautious for costs for one/two op general shuffles - VSHUFPD doesn't have to replicate the same shuffle in both lanes like VSHUFPS does.
llvm-svn: 335216
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second src
llvm-svn: 334698
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the elements come from the second src
llvm-svn: 334623
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second src
llvm-svn: 334620
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the elements come from the second src
llvm-svn: 334616
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(PR33744)
As discussed on PR33744, this patch relaxes ShuffleKind::SK_Alternate which requires shuffle masks to only match an alternating pattern from its 2 sources:
e.g. v4f32: <0,5,2,7> or <4,1,6,3>
This seems far too restrictive as most SIMD hardware which will implement it using a general blend/bit-select instruction, so replaces it with SK_Select, permitting elements from either source as long as they are inline:
e.g. v4f32: <0,5,2,7>, <4,1,6,3>, <0,1,6,7>, <4,1,2,3> etc.
This initial patch just updates the name and cost model shuffle mask analysis, later patch reviews will update SLP to better utilise this - it still limits itself to SK_Alternate style patterns.
Differential Revision: https://reviews.llvm.org/D47985
llvm-svn: 334513
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As discussed on D47985, identity shuffle masks should probably be free.
I've limited this to the case where the input and output types all match - but we could probably accept all cases.
Differential Revision: https://reviews.llvm.org/D47986
llvm-svn: 334506
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llvm-svn: 334486
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llvm-svn: 334351
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Similar to v4i32 SHL, convert v8i16 shift amounts to scale factors instead to improve performance and reduce instruction count. We were already doing this for constant shifts, this adds variable shift support.
Reduces the serial nature of the codegen, which relies on chains of plendvb/pand+pandn+por shifts.
This is a step towards adding support for vXi16 vector rotates.
Differential Revision: https://reviews.llvm.org/D47546
llvm-svn: 334023
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TargetTransformInfo::getInstructionThroughput
This enables us to detect more fast path sdiv cases under cost analysis.
This patch also enables us to handle non-uniform-constant pow2 cases for X86 SDIV costs.
Found while working on D46276
Future patches can then extend the vectorizers to more fully support non-uniform pow2 cases.
Differential Revision: https://reviews.llvm.org/D46637
llvm-svn: 332969
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A future patch will require this and the diff is much better if we perform the split separately.
llvm-svn: 331867
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llvm-svn: 330852
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llvm-svn: 330439
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llvm-svn: 330436
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llvm-svn: 330435
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llvm-svn: 330433
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Just reuses goldmont costs atm
llvm-svn: 330432
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We're mostly testing with generic isa attributes, but PR36550 will require testing of specific target's scheduler models as well.
llvm-svn: 330056
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Was proving cumbersome to test with/without fma
llvm-svn: 330054
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llvm-svn: 330052
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llvm-svn: 330051
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llvm-svn: 330050
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update_analyze_test_checks.py
NOTE: We're only really interested in the extractelement cost (which represents the entire reduction).
llvm-svn: 329504
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update_analyze_test_checks.py
llvm-svn: 329502
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update_analyze_test_checks.py
llvm-svn: 329500
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update_analyze_test_checks.py
llvm-svn: 329499
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llvm-svn: 329498
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update_analyze_test_checks.py
llvm-svn: 329497
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update_analyze_test_checks.py
llvm-svn: 329413
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update_analyze_test_checks.py
llvm-svn: 329410
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update_analyze_test_checks.py
llvm-svn: 329407
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update_analyze_test_checks.py
llvm-svn: 329402
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update_analyze_test_checks.py
llvm-svn: 329401
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update_analyze_test_checks.py
llvm-svn: 329400
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update_analyze_test_checks.py
llvm-svn: 329398
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generation
The script allows the auto-generation of checks for cost model tests to speed up their creation and help improve coverage, which will help a lot with PR36550.
If the need arises we can add support for other analyze passes as well, but the cost models was the one I needed to get done - at the moment it just warns that any other analysis mode is unsupported.
I've regenerated a couple of x86 test files to show the effect.
Differential Revision: https://reviews.llvm.org/D45272
llvm-svn: 329390
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shuffle costs
llvm-svn: 329168
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Add fdiv costs for Goldmont using table 16-17 of the Intel Optimization Manual. Also add overrides for FSQRT for Goldmont and Silvermont.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44644
llvm-svn: 328451
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