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* [Attributor] H2S fix.Stefan Stipanovic2019-12-171-2/+2
| | | | | | | | | | Summary: Fixing issues that were noticed in D71521 Reviewers: jdoerfert, lebedev.ri, uenoku Subscribers: Differential Revision: https://reviews.llvm.org/D71564
* [AMDGPU] Fix typo in SIInstrInfo::memOpsHaveSameBasePtrJay Foad2019-12-171-1/+1
| | | | | | | | | | | | | | | Summary: The typo has been present since memOpsHaveSameBasePtr was introduced in r313208. It caused SIInstrInfo::shouldClusterMemOps to cluster more mem ops than it was supposed to. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71616
* [SDAG] adjust isNegatibleForFree calculation to avoid crashingSanjay Patel2019-12-171-1/+8
| | | | | | | | | | | | | | | | | | | | This is an alternate fix for the bug discussed in D70595. This also includes minimal tests for other in-tree targets to show the problem more generally. We check the number of uses as a predicate for whether some value is free to negate, but that use count can change as we rewrite the expression in getNegatedExpression(). So something that was marked free to negate during the cost evaluation phase becomes not free to negate during the rewrite phase (or the inverse - something that was not free becomes free). This can lead to a crash/assert because we expect that everything in an expression that is negatible to be handled in the corresponding code within getNegatedExpression(). This patch adds a hack to work-around the case where we probably no longer detect that either multiply operand of an FMA isNegatibleForFree which is assumed to be true when we started rewriting the expression. Differential Revision: https://reviews.llvm.org/D70975
* Revert "[SDAG] remove use restriction in isNegatibleForFree() when called ↵Sanjay Patel2019-12-171-8/+1
| | | | | | | from getNegatedExpression()" This reverts commit 36b1232ec5f370ab9fe8fcff0458d2fca5ca9b7f. Need to adjust commit message - that was a leftover from the earlier version.
* [SDAG] remove use restriction in isNegatibleForFree() when called from ↵Sanjay Patel2019-12-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | getNegatedExpression() This is an alternate fix for the bug discussed in D70595. This also includes minimal tests for other in-tree targets to show the problem more generally. We check the number of uses as a predicate for whether some value is free to negate, but that use count can change as we rewrite the expression in getNegatedExpression(). So something that was marked free to negate during the cost evaluation phase becomes not free to negate during the rewrite phase (or the inverse - something that was not free becomes free). This can lead to a crash/assert because we expect that everything in an expression that is negatible to be handled in the corresponding code within getNegatedExpression(). This patch adds a hack to work-around the case where we probably no longer detect that either multiply operand of an FMA isNegatibleForFree which is assumed to be true when we started rewriting the expression. Differential Revision: https://reviews.llvm.org/D70975
* [RISCV] Add subtargets initialized with target featureZakk Chen2019-12-172-6/+31
| | | | | | | | | | | | expected failed test (RV32IF-ILP32F) will be fixed in a subsequent patch. Reviewers: efriedma, lenary, asb Reviewed By: efriedma, lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70116
* [DAGCombiner] Add node back in the worklist in topological order in ↵Amaury Séchet2019-12-171-2/+1
| | | | | | | | | | | | | | | | | CommitTargetLoweringOpt Summary: Right now, DAGCombiner process the nodes in an iplementation defined order. This tends to be fragile as optimisation may or may not kick in depending on the traversal order. This is part of a larger effort to get the DAGCombiner to process its node in topological order. Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70921
* [SystemZ][FPEnv] Back-end support for STRICT_[SU]INT_TO_FPUlrich Weigand2019-12-173-16/+31
| | | | | | | | | As of b1d8576 there is middle-end support for STRICT_[SU]INT_TO_FP, so this patch adds SystemZ back-end support as well. The patch is SystemZ target specific except for adding SD patterns strict_[su]int_to_fp and any_[su]int_to_fp to TargetSelectionDAG.td as usual.
* [InstCombine][AMDGPU] Trim more components of *buffer_loadPiotr Sobczak2019-12-171-17/+60
| | | | | | | | | | | | | | Summary: Add trimming of unused components of s_buffer_load. Extend trimming of *buffer_load to also include unused components at the beginning of vectors and update offset. Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70315
* [ MC ] Match labels to existing fragments even when switching sections.Michael Trent2019-12-172-13/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This commit builds upon Derek Schuff's 2014 commit for attaching labels to existing fragments ( Diff Revision: http://reviews.llvm.org/D5915 ) When temporary labels appear ahead of a fragment, MCObjectStreamer will track the temporary label symbol in a "Pending Labels" list. Labels are associated with fragments when a real fragment arrives; otherwise, an empty data fragment will be created if the streamer's section changes or if the stream finishes. This commit moves the "Pending Labels" list into each MCStream, so that this label-fragment matching process is resilient to section changes. If the streamer emits a label in a new section, switches to another section to do other work, then switches back to the first section and emits a fragment, that initial label will be associated with this new fragment. Labels will only receive empty data fragments in the case where no other fragment exists for that section. The downstream effects of this can be seen in Mach-O relocations. The previous approach could produce local section relocations and external symbol relocations for the same data in an object file, and this mix of relocation types resulted in problems in the ld64 Mach-O linker. This commit ensures relocations triggered by temporary labels are consistent. Reviewers: pete, ab, dschuff Reviewed By: pete, dschuff Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71368
* Revert "Honor -fuse-init-array when os is not specified on x86"Mitch Phillips2019-12-1711-4/+63
| | | | | | | This reverts commit aa5ee8f244441a8ea103a7e0ed8b6f3e74454516. This change broke the sanitizer buildbots. See comments at the patchset (https://reviews.llvm.org/D71360) for more information.
* This adds constrained intrinsics for the signed and unsigned conversionsKevin P. Neal2019-12-178-89/+395
| | | | | | | | | of integers to floating point. This includes some of Craig Topper's changes for promotion support from D71130. Differential Revision: https://reviews.llvm.org/D69275
* PostRA Machine Sink should take care of COPY defining register that is a ↵alex-t2019-12-171-3/+7
| | | | | | sub-register by another COPY source operand Differential Revision: https://reviews.llvm.org/D71132
* [DebugInfo] Only print a single blank line after an empty line tableJames Henderson2019-12-171-1/+1
| | | | | | | | | | | | Commit 84a9756 added an extra blank line at the end of any line table. However, a blank line is also printed after the line table header, which meant that two blank lines in a row were being printed after a header, if there were no rows. This patch defers the post-header blank line printing until it has been determined that there are rows to print. Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D71540
* [RISCV][NFC] Trivial cleanupLuís Marques2019-12-171-3/+0
| | | | Fix a typo. Remove two seemingly out-of-date TODO comments.
* Fix assertion failure in getMemOperandWithOffsetWidthKristof Beyls2019-12-177-30/+36
| | | | | | | | | | | | | | | | | | | | This fixes an assertion failure that triggers inside getMemOperandWithOffset when Machine Sinking calls it on a MachineInstr that is not a memory operation. Different backends implement getMemOperandWithOffset differently: some return false on non-memory MachineInstrs, others assert. The Machine Sinking pass in at least SinkingPreventsImplicitNullCheck relies on getMemOperandWithOffset to return false on non-memory MachineInstrs, instead of asserting. This patch updates the documentation on getMemOperandWithOffset that it should return false on any MachineInstr it cannot handle, instead of asserting. It also adapts the in-tree backends accordingly where necessary. Differential Revision: https://reviews.llvm.org/D71359
* Resubmit "[Alignment][NFC] Deprecate CreateMemCpy/CreateMemMove"Guillaume Chatelet2019-12-1713-116/+119
| | | | | | | | | | | | | | | | | | | | Summary: This is a resubmit of D71473. This patch introduces a set of functions to enable deprecation of IRBuilder functions without breaking out of tree clients. Functions will be deprecated one by one and as in tree code is cleaned up. This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: aaron.ballman, courbet Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71547
* Revert "[Support] Fix time trace multi threaded support with ↵Russell Gallop2019-12-171-1/+2
| | | | | | | | | LLVM_ENABLE_THREADS=OFF" This reverts commit 2bbcf156acc157377e814fbb1828a9fe89367ea2. This was failing on systems which use __thread such as http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/30851
* [Support] Fix time trace multi threaded support with LLVM_ENABLE_THREADS=OFFRussell Gallop2019-12-171-2/+1
| | | | | | | Following on from 8ddcd1dc26ba, which added the support. As pointed out on D71059 this does not build on some systems with LLVM_ENABLE_THREADS=OFF. Differential Revision: https://reviews.llvm.org/D71548
* [ObjC][DWARF] Emit DW_AT_APPLE_objc_direct for methods marked as ↵Raphael Isemann2019-12-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | __attribute__((objc_direct)) Summary: With DWARF5 it is no longer possible to distinguish normal methods and methods with `__attribute__((objc_direct))` by just looking at the debug information as they are both now children of the of the DW_TAG_structure_type that defines them (before only the `__attribute__((objc_direct))` methods were children). This means that in LLDB we are no longer able to create a correct Clang AST of a module by just looking at the debug information. Instead we would need to call the Objective-C runtime to see which of the methods have a `__attribute__((objc_direct))` and then add the attribute to our own Clang AST depending on what the runtime returns. This would mean that we either let the module AST be dependent on the Objective-C runtime (which doesn't seem right) or we retroactively add the missing attribute to the imported AST in our expressions. A third option is to annotate methods with `__attribute__((objc_direct))` as `DW_AT_APPLE_objc_direct` which is what this patch implements. This way LLDB doesn't have to call the runtime for any `__attribute__((objc_direct))` method and the AST in our module will already be correct when we create it. Reviewers: aprantl, SouraVX Reviewed By: aprantl Subscribers: hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm, #debug-info Differential Revision: https://reviews.llvm.org/D71201
* [LegalizeTypes] Pre-size the SmallVectors in ScalarizeVecRes_StrictFPOp and ↵Craig Topper2019-12-161-9/+9
| | | | | | SplitVecRes_StrictFPOp so we don't have to call push_back. NFCI This avoids grow checking/handling in each iteration of the loop.
* [LegalizeTypes] Remove ScalarizeVecRes_STRICT_FP_ROUND in favor of just ↵Craig Topper2019-12-162-16/+0
| | | | | | | | using ScalarizeVecRes_StrictFPOp. NFCI It looks like ScalarizeVecRes_StrictFPOp can handle a variable number of arguments with scalar and vector types so it should be sufficient.
* [LegalizeTypes] Remove the call to SplitVecRes_UnaryOp from ↵Craig Topper2019-12-161-29/+0
| | | | | | | | SplitVecRes_StrictFPOp. NFCI It doesn't seem to do anything that SplitVecRes_StrictFPOp can't do. SplitVecRes_StrictFPOp already handles nodes with a variable number of arguments and a mix of scalar and vector arguments.
* [MC] Delete redundant alignment update from MCELFStreamer::EmitCommonSymbol. NFCFangrui Song2019-12-161-4/+0
| | | | EmitValueToAlignment() updates the maximum alignment.
* Revert "[LoopUtils] Updated deleteDeadLoop() to handle loop nest."Whitney Tsang2019-12-171-12/+1
| | | | | This reverts commit cd09fee3d63296dd2df0bbb1fae363ca9f311d44. This reverts commit c066ff11d84a7797503ad5a44c4129136926dc85.
* [Attributor][NFC] Clang format the AttributorJohannes Doerfert2019-12-161-11/+11
| | | | | | | The Attributor is always kept formatted so diffs are cleaner. Sometime we get out of sync for various reasons so we need to format the file once in a while.
* [SelectionDAG] Add the fpexcept flag to the SelectionDAG dumping output so ↵Craig Topper2019-12-161-0/+3
| | | | | | | | we can better see when its not propagating. We're currently losing this flag in type legalization and probably other places when we expand strict fp nodes. This will make reading logs easier.
* [LoopUtils] Updated deleteDeadLoop() to handle loop nest.Whitney Tsang2019-12-171-1/+12
| | | | | | | | | Reviewer: kariddi, sanjoy, reames, Meinersbur, bmahjour, etiotto, kbarton Reviewed By: Meinersbur Subscribers: mgorny, hiraditya, llvm-commits Tag: LLVM Differential Revision: https://reviews.llvm.org/D70939
* [NFC][llvm][MIRVRegNamerUtils] Moving some switch cases and altering comments.Puyan Lotfi2019-12-161-5/+5
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* [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.Puyan Lotfi2019-12-161-2/+7
| | | | | | | | | | | | | | | | | This patch makes it so that cases where multiple instructions that differ only in their ConstantInt or ConstantFP MachineOperand values no longer collide. For instance: %0:_(s1) = G_CONSTANT i1 true %1:_(s1) = G_CONSTANT i1 false %2:_(s32) = G_FCONSTANT float 1.0 %3:_(s32) = G_FCONSTANT float 0.0 Prior to this patch the first two instructions would collide together. Also, the last two G_FCONSTANT instructions would also collide. Now they will no longer collide. Differential Revision: https://reviews.llvm.org/D71558
* Honor -fuse-init-array when os is not specified on x86Kamlesh Kumar2019-12-1611-63/+4
| | | | | | | | | | | | | | | | | | | | | Currently -fuse-init-array option is not effective when target triple does not specify os, on x86,x86_64. i.e. // -fuse-init-array is not honored. $ clang -target i386 -fuse-init-array test.c -S // -fuse-init-array is honored. $ clang -target i386-linux -fuse-init-array test.c -S This patch fixes first case. And does cleanup. Reviewers: rnk, craig.topper, fhahn, echristo Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D71360
* [RISCV] Added isCompressibleInst() to estimate size in getInstSizeInBytes()Ana Pazos2019-12-161-1/+15
| | | | | | | | | | | | | | | | | | | Summary: Modified compression emitter tablegen backend to emit isCompressibleInst() check which in turn is used by getInstSizeInBytes() to better estimate instruction size. Note the generation of compressed instructions in RISC-V happens late in the assembler therefore instruction size estimate might be off if computed before. Reviewers: lenary, asb, luismarques, lewis-revill Reviewed By: asb Subscribers: sameer.abuasal, lewis-revill, hiraditya, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, lenary, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68290
* [AArch64][SVE] Change pattern generation code to fix -Wimplicit-fallthrough ↵Fangrui Song2019-12-161-4/+11
| | | | after D71483
* [AArch64][SVE] Add patterns for logical immediate operations.Danilo Carvalho Grael2019-12-163-4/+56
| | | | | | | | | | | | | | Summary: Add pattern matching for the following SVE logical vector and immediate instructions: - and/bic, orr/orn, eor/eon. Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan Tags: #llvm Differential Revision: https://reviews.llvm.org/D71483
* [LoopFusion] Restrict loop fusion to rotated loops.Kit Barton2019-12-161-0/+6
| | | | | | | | | | | | | | | | Summary: This patch restricts loop fusion to only consider rotated loops as valid candidates. This simplifies the analysis and transformation and aligns with other loop optimizations. Reviewers: jdoerfert, Meinersbur, dmgreen, etiotto, Whitney, fhahn, hfinkel Reviewed By: Meinersbur Subscribers: ormris, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71025
* [InstCombine] Teach removeBitcastsFromLoadStoreOnMinMax not to change the ↵Craig Topper2019-12-161-5/+14
| | | | | | | | | | size of a store. We can change the type as long as we don't change the size. Fixes PR44306 Differential Revision: https://reviews.llvm.org/D71532
* [WebAssembly] Replace SIMD int min/max builtins with patternsThomas Lively2019-12-162-4/+11
| | | | | | | | | | | | | | | | | | Summary: The instructions were originally implemented via builtins and intrinsics so users would have to explicitly opt-in to using them. This was useful while were validating whether these instructions should have been merged into the spec proposal. Now that they have been, we can use normal codegen patterns, so the intrinsics and builtins are no longer useful. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71500
* [SystemZ] Improve verification of MachineOperands.Jonas Paulsson2019-12-163-8/+40
| | | | | | | | | | | Now that the machine verifier will check for cases of register/immediate MachineOperands and their correspondence to the MC instruction descriptor, this patch adds the operand types to the descriptors where they were previously missing. All MCOI::OPERAND_UNKNOWN operand types have been handled to get a known type, except for G_... (global isel) instructions. Review: Ulrich Weigand https://reviews.llvm.org/D71494
* [TLI] Support for per-Function TLI that overrides available libfuncsTeresa Johnson2019-12-161-18/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Follow-on to D66428 and D71193, to build the TLI per-function so that -fno-builtin* handling can be migrated to use function attributes. See discussion on D61634 for background. This is an enabler for fixing handling of these options for LTO, for example. With D71193, the -fno-builtin* flags are converted to function attributes, so we can now set this information per-function on the TLI. In this patch, the TLI constructor is changed to take a Function, which can be used to override the available builtins. The TLI is augmented with an array that can be used to specify which builtins are not available for the corresponding function. The available function checks are changed to consult this override before checking the underlying module level baseline TLII. New code is added to set this override array based on the attributes. I also removed the code that sets availability in the TLII in clang from the options, which is no longer needed. I removed a per-Triple caching of TLII objects in the analysis object, as it is based on the Module's Triple which is the same for all functions in any case. Is there a case where we would be compiling multiple Modules with different Triples in one compilation? Finally, I have changed the legacy analysis wrapper to create and use the new PM analysis class (TargetLibraryAnalysis) in getTLI. This is consistent with the behavior of getTTI for the legacy TargetTransformInfo analysis. This change means that getTLI now creates a new TLI on each call (although that should be very cheap as we cache the module level TLII, and computing the per-function attribute based availability should also be reasonably efficient). I measured the compile time for a large C++ file with tens of thousands of functions and as expected there was no increase. Reviewers: chandlerc, hfinkel, gchatelet Subscribers: mehdi_amini, dexonsmith, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67923
* [mips] Add an assert in getTargetStreamer()Miloš Stojanović2019-12-161-0/+2
| | | | | | Check if the TargetStreamer can be accessed. Differential Revision: https://reviews.llvm.org/D71477
* Revert "[Alignment][NFC] Deprecate CreateMemCpy/CreateMemMove"Guillaume Chatelet2019-12-1613-119/+116
| | | | This reverts commit 181ab91efc9fb08dedda10a2fbc5fccb83ce8799.
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-161-8/+304
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Reland after fixing a bug that allowed outlining of SP modifying instructions that invalidated return address signing. During AArch64 frame lowering instructions to enable return address signing are inserted into functions if needed. Functions generated during machine outlining don't run through target frame lowering and hence are missing such instructions. This patch introduces the following changes: 1. If not all functions that potentially participate in function outlining agree on their return address signing scope and their return address signing key, outlining is disabled for these functions. 2. If not all functions that potentially participate in function outlining agree on their support for v8.3A features, outlining is disabled for these functions. 3. If an outlining candidate would outline instructions that modify sp in a way that invalidates return address signing, outlining is disabled for that particular candidate. 4. If all candidate functions agree on the signing scope, signing key and their support for v8.3 features, the outlined function behaves as if it had the same scope and key attributes and as if it would provide the same v8.3A support as the original functions. Reviewers: ostannard, paquette Reviewed By: ostannard Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70635
* [Alignment][NFC] Deprecate CreateMemCpy/CreateMemMoveGuillaume Chatelet2019-12-1613-116/+119
| | | | | | | | | | | | | | | | | | Summary: This patch introduces a set of functions to enable deprecation of IRBuilder functions without breaking out of tree clients. Functions will be deprecated one by one and as in tree code is cleaned up. This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, jvesely, nhaehnle, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71473
* [AArch64][SVE2] Add intrinsics for binary narrowing operationsAndrzej Warzynski2019-12-162-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The following intrinsics for binary narrowing add and sub operations are added: * @llvm.aarch64.sve.addhnb * @llvm.aarch64.sve.addhnt * @llvm.aarch64.sve.raddhnb * @llvm.aarch64.sve.raddhnt * @llvm.aarch64.sve.subhnb * @llvm.aarch64.sve.subhnt * @llvm.aarch64.sve.rsubhnb * @llvm.aarch64.sve.rsubhnt Reviewers: sdesmalen, rengolin, efriedma Reviewed By: sdesmalen, efriedma Subscribers: tschuett, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71424
* [AArch64] Enable emission of stack maps for non-Mach-O binaries on AArch64.Kristof Beyls2019-12-161-1/+1
| | | | | | | | | | The emission of stack maps in AArch64 binaries has been disabled for all binary formats except Mach-O since rL206610, probably mistakenly, as far as I can tell. This patch reverts this to its intended state. Differential Revision: https://reviews.llvm.org/D70069 Patch by Loic Ottet.
* [Aarch64][SVE] Add intrinsics for scatter storesAndrzej Warzynski2019-12-165-61/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds the following SVE intrinsics for scatter stores: * 64-bit offsets: * @llvm.aarch64.sve.st1.scatter (unscaled) * @llvm.aarch64.sve.st1.scatter.index (scaled) * 32-bit unscaled offsets: * @llvm.aarch64.sve.st1.scatter.uxtw (zero-extended offset) * @llvm.aarch64.sve.st1.scatter.sxtw (sign-extended-offset) * 32-bit scaled offsets: * @llvm.aarch64.sve.st1.scatter.uxtw.index (zero-extended offset) * @llvm.aarch64.sve.st1.scatter.sxtw.index (sign-extended offset) * vector base + immediate: * @llvm.aarch64.sve.st1.scatter.imm Reviewers: rengolin, efriedma, sdesmalen Reviewed By: efriedma, sdesmalen Subscribers: kmclaughlin, eli.friedman, tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71074
* Fix whitespace.Jay Foad2019-12-161-2/+2
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* [BasicBlockUtils] Fix dbg.value elimination problem in MergeBlockIntoPredecessorBjorn Pettersson2019-12-161-14/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In commit d60f34c20a2f31335c8d5626e (llvm-svn 317128, PR35113) MergeBlockIntoPredecessor was changed into discarding some dbg.value intrinsics referring to PHI values, post-splice due to loop rotation. That elimination of dbg.value intrinsics did not consider which dbg.value to keep depending on the context (e.g. if the variable is changing its value several times inside the basic block). In the past that hasn't been such a big problem since CodeGenPrepare::placeDbgValues has moved the dbg.value to be next to the PHI node anyway. But after commit 00e238896cd8ad3a7d7 CodeGenPrepare isn't doing that any longer, so we need to be more careful when avoiding duplicate dbg.value intrinsics in MergeBlockIntoPredecessor. This patch replaces the code that tried to avoid duplicate dbg.values by using the RemoveRedundantDbgInstrs helper. Reviewers: aprantl, jmorse, vsk Reviewed By: aprantl, vsk Subscribers: jholewinski, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71480
* [BasicBlockUtils] Add utility to remove redundant dbg.value instrsBjorn Pettersson2019-12-163-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a RemoveRedundantDbgInstrs to BasicBlockUtils with the goal to remove redundant dbg intrinsics from a basic block. This can be useful after various transforms, as it might be simpler to do a filtering of dbg intrinsics after the transform than during the transform. One primary use case would be to replace a too aggressive removal done by MergeBlockIntoPredecessor, seen at loop rotate (not done in this patch). The elimination algorithm currently focuses on dbg.value intrinsics and is doing two iterations over the BB. First we iterate backward starting at the last instruction in the BB. Whenever a consecutive sequence of dbg.value instructions are found we keep the last dbg.value for each variable found (variable fragments are identified using the {DILocalVariable, FragmentInfo, inlinedAt} triple as given by the DebugVariable helper class). Next we iterate forward starting at the first instruction in the BB. Whenever we find a dbg.value describing a DebugVariable (identified by {DILocalVariable, inlinedAt}) we save the {DIValue, DIExpression} that describes that variables value. But if the variable already was mapped to the same {DIValue, DIExpression} pair we instead drop the second dbg.value. To ease the process of making lit tests for this utility a new pass is introduced called RedundantDbgInstElimination. It can be executed by opt using -redundant-dbg-inst-elim. Reviewers: aprantl, jmorse, vsk Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71478
* Fix for AMDGPU MUL_I24 known bits calculationJay Foad2019-12-161-9/+8
| | | | | | | | | | | | | | | | | | | Summary: At present, the code calculating known bits of AMDGPU MUL_I24 confuses the concepts of "non-negative number" and "positive number". In some situations, it results in incorrect code. I have a case where the optimizer replaces the result of calculating MUL_I24(-5, 0) with -8. Reviewers: foad, arsenm Reviewed By: arsenm Subscribers: foad, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Patch by Eugene Kuznetsov. Differential Revision: https://reviews.llvm.org/D70367
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