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* [AMDGPU] Implemented fma cost analysisStanislav Mekhanoshin2019-12-182-0/+53
| | | | Differential Revision: https://reviews.llvm.org/D71676
* Enable STRICT_FP_TO_SINT/UINT on X86 backendLiu, Chen32019-12-196-118/+222
| | | | | | This patch is mainly for custom lowering the vector operation. Differential Revision: https://reviews.llvm.org/D71592
* [PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep passczhengsz2019-12-181-5/+9
| | | | | | | | Fix a FIXME in ppcloopinstrformprep pass. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D71346
* DebugInfo: Include DW_AT_base_addr even in gmlt with no inline functionsDavid Blaikie2019-12-181-1/+1
| | | | | | | | | Since the address pool doesn't get populated in this case (due to the lack of inlining, no child DIEs are added to the CU - so no addresses are needed for the DIEs themselves) until the range list is emitted - at the time the attributes are added to the CU, the address pool is empty. So check whether the address pool will be used for the range lists & add an addr_base if that's the case.
* DebugInfo: Don't use implicit zero addr_baseDavid Blaikie2019-12-182-7/+10
| | | | (found when LLVM fails to emit addr_base for gmlt+DWARFv5)
* Reapply "NFC: DebugInfo: Refactor RangeSpanList to be a struct, like ↵David Blaikie2019-12-184-19/+11
| | | | | | | | | | | | | | | DebugLocStream::List" Move these data structures closer together so their emission code can eventually share more of its implementation. Was an egregious bug (completely untested, evidently) where I hadn't inverted a DWARFv5 test as needed, so it was doing the exact opposite of what was required & thus tried to emit a DWARFv5 range list header in DWARFv4. Reapply 8e04896288d22ed8bef7ac367923374f96b753d6 which was reverted in a8154e5e0c83d2f0f65f3b4fb1a0bc68785bd975.
* [WebAssembly] Add avgr_u intrinsics and require nuw in patternsThomas Lively2019-12-181-16/+17
| | | | | | | | | | | | | | | | | | Summary: The vector pattern `(a + b + 1) / 2` was previously selected to an avgr_u instruction regardless of nuw flags, but this is incorrect in the case where either addition may have an unsigned wrap. This CL changes the existing pattern to require both adds to have nuw flags and adds builtin functions and intrinsics for the avgr_u instructions because the corrected pattern is not representable in C. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71648
* Revert "[Orc][LLJIT] Use JITLink even if a custom JITTargetMachineBuilder is ↵Lang Hames2019-12-181-7/+3
| | | | | | | | supplied." This reverts commit 298e183e813c884dd22816383405bae3ef9ef278. This commit caused some build failures -- reverting while I investigate.
* [X86] Add a simple hack to IsProfitableToFold to prevent vselect+strict fp ↵Craig Topper2019-12-181-0/+6
| | | | | | | | operations from being folded into masked instructions. We really need to update the isel patterns to prevent this, but that requires some tablegen de-tangling. So this hack will work for correctness in the short term.
* [Orc][LLJIT] Use JITLink even if a custom JITTargetMachineBuilder is supplied.Lang Hames2019-12-181-3/+7
| | | | | | LLJITBuilder will now use JITLink on supported platforms even if a custom JITTargetMachineBuilder is supplied, provided that neither the code model, nor the relocation model, nor the ObjectLinkingLayerCreator is set.
* Revert "[InstCombine][AMDGPU] Trim more components of *buffer_load"Piotr Sobczak2019-12-181-60/+17
| | | | | | Revert D70315, as it breaks gfx8 for some reason. This reverts commit 65f94b33808d7d69539961a6f5a2168f0a1eef41.
* [FPEnv] Strict versions of llvm.minimum/llvm.maximumUlrich Weigand2019-12-183-2/+6
| | | | | | | | | | | | | Add new intrinsics llvm.experimental.constrained.minimum llvm.experimental.constrained.maximum as strict versions of llvm.minimum and llvm.maximum. Includes SystemZ back-end support. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D71624
* [LoopFusion] Use the LoopInfo::isRotatedForm method (NFC).Kit Barton2019-12-181-15/+3
| | | | | | Loop fusion previously had a method to check whether a loop was in rotated form. This method has been moved into the LoopInfo class. This patch removes the old isRotated method from loop fusion, in favour of the new one in LoopInfo.
* [InstCombine] Insert instructions before adding them to worklistJakub Kuderski2019-12-182-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch adds instructions to the InstCombine worklist after they are properly inserted. This way we don't get `<badref>`s printed when logging added instructions. It also adds a check in `Worklist::Add` that ensures that all added instructions have parents. Simple test case that illustrates the difference when run with `--debug-only=instcombine`: ``` define i32 @test35(i32 %a, i32 %b) { %1 = or i32 %a, 1135 %2 = or i32 %1, %b ret i32 %2 } ``` Before this patch: ``` INSTCOMBINE ITERATION #1 on test35 IC: ADDING: 3 instrs to worklist IC: Visiting: %1 = or i32 %a, 1135 IC: Visiting: %2 = or i32 %1, %b IC: ADD: %2 = or i32 %a, %b IC: Old = %3 = or i32 %1, %b New = <badref> = or i32 %2, 1135 IC: ADD: <badref> = or i32 %2, 1135 ... ``` With this patch: ``` INSTCOMBINE ITERATION #1 on test35 IC: ADDING: 3 instrs to worklist IC: Visiting: %1 = or i32 %a, 1135 IC: Visiting: %2 = or i32 %1, %b IC: ADD: %2 = or i32 %a, %b IC: Old = %3 = or i32 %1, %b New = <badref> = or i32 %2, 1135 IC: ADD: %3 = or i32 %2, 1135 ... ``` Reviewers: fhahn, davide, spatel, foad, grosser, nikic Reviewed By: nikic Subscribers: nikic, lebedev.ri, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71093
* Fix more VFS tests on WindowsAdrian McCarthy2019-12-181-10/+33
| | | | | | | | | | | | Since VFS paths can be in either Posix or Windows style, we have to use a more flexible definition of "absolute" path. The key here is that FileSystem::makeAbsolute is now virtual, and the RedirectingFileSystem override checks for either concept of absolute before trying to make the path absolute by combining it with the current directory. Differential Revision: https://reviews.llvm.org/D70701
* Revert "[AArch64][SVE] Replace integer immediate intrinsics with splat ↵Danilo Carvalho Grael2019-12-182-39/+22
| | | | | | | | | | vector variant" This reverts commit 830e08b98bcb427136443093c282b25328137cf0 and eb1857ce0da481caf82271e6d0c9fc745dfab26f. This commit leads to an unexpected failure on test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll. The review will need more changes before its re-commited.
* [Clang FE, SystemZ] Don't add "true" value for the "mnop-mcount" attribute.Jonas Paulsson2019-12-182-3/+2
| | | | | | | | Let the "mnop-mcount" function attribute simply be present or non-present. Update SystemZ backend as well to use hasFnAttribute() instead. Review: Ulrich Weigand https://reviews.llvm.org/D71669
* [InstCombine] Allow to limit the max number of iterationsJakub Kuderski2019-12-181-9/+50
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch teaches InstCombine to accept a new parameter: maximum number of iterations over functions. InstCombine tries to simplify instructions by iterating over the whole function until the function stops changing. As a consequence, the last iteration before reaching a fixpoint visits all instructions in the worklist and never performs any rewrites. Bounding the number of iterations can have 2 benefits: * In case the users of the pass can make a good guess about the number of required iterations, we can save the time normally spent on the last iteration that doesn't change anything. * When the wants to use InstCombine as a cleanup pass, it may be enough to run just a few iterations and stop even before reaching a fixpoint. This can be also useful for implementing a lightweight pass pipeline (think `-O1`). This patch does not change the behavior of opt or Clang -- limiting the number of iterations is entirely opt-in. Reviewers: fhahn, davide, spatel, foad, nlopes, grosser, lebedev.ri, nikic, xbolva00 Reviewed By: spatel Subscribers: craig.topper, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71145
* llvm-cxxmap: fix support for remapping non-mangled names.Richard Smith2019-12-181-6/+22
| | | | | | | Remappings involving extern "C" names were already supported in the context of <local-name>s, but this support didn't work for remapping the complete mangling itself. (Eg, we would remap X<foo> but not foo itself, if foo is an extern "C" function.)
* [SelectionDAGBuilder] Use getConstant instead of getTargetConstant to build ↵Craig Topper2019-12-181-2/+2
| | | | | | | | | | | | the offset for struct types in getUniformBase. getTargetConstant prevents any optimizations from operating on the value and basically says its already been iseled. But since we want the index to be in a register, this isn't true. Prior to this we were generating a vbroadcast with an immediate argument which is illegal and was flagged by the expensive checks bot.
* [PowerPC][NFC] Refactor splat of constant to vector.Stefan Pintilie2019-12-181-25/+4
| | | | | | | | | Refactor the splatting of a constant to a vector so that common code is used both for Power9 and Power8. Patch by: Anil Mahmud Differential Revision: https://reviews.llvm.org/D71481
* [AArch64][SVE] Replace integer immediate intrinsics with splat vector variantDanilo Carvalho Grael2019-12-182-22/+39
| | | | | | | | | | | | Summary: Replace the integer immediate intrisics with splat vector variants so they can be applied as optimizations for the C/C++ intrinsics. Reviewers: sdesmalen, huntergr, rengolin, efriedma, c-rhodes, mgudim, kmclaughlin Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan Tags: #llvm Differential Revision: https://reviews.llvm.org/D71614
* [ MC ] Match labels to existing fragments even when switching sections.Michael Trent2019-12-182-14/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This commit restores the original branch (4272372c571) and applies an additional change dropped from the original in a bad merge. This change should address the previous bot failures. Both changes reviewed by pete.) Summary: This commit builds upon Derek Schuff's 2014 commit for attaching labels to existing fragments ( Diff Revision: http://reviews.llvm.org/D5915 ) When temporary labels appear ahead of a fragment, MCObjectStreamer will track the temporary label symbol in a "Pending Labels" list. Labels are associated with fragments when a real fragment arrives; otherwise, an empty data fragment will be created if the streamer's section changes or if the stream finishes. This commit moves the "Pending Labels" list into each MCStream, so that this label-fragment matching process is resilient to section changes. If the streamer emits a label in a new section, switches to another section to do other work, then switches back to the first section and emits a fragment, that initial label will be associated with this new fragment. Labels will only receive empty data fragments in the case where no other fragment exists for that section. The downstream effects of this can be seen in Mach-O relocations. The previous approach could produce local section relocations and external symbol relocations for the same data in an object file, and this mix of relocation types resulted in problems in the ld64 Mach-O linker. This commit ensures relocations triggered by temporary labels are consistent. Reviewers: pete, ab, dschuff Reviewed By: pete, dschuff Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71368
* Reapply: [DebugInfo] Correctly handle salvaged casts and split fragments at ISelstozer2019-12-183-11/+45
| | | | | | | | This reverts commit 1f3dd83cc1f2b8f72b9d59e2b4221b12fb7f9a95, reapplying commit bb1b0bc4e57428ce364d3d6c075ff03cb8973462. The original commit failed on some builds seemingly due to the use of a bracketed constructor with an std::array, i.e. `std::array<> arr({...})`.
* [NFC][InlineCost] Run clang-format on InlineCost.cppMircea Trofin2019-12-181-11/+10
| | | | | | | | | | | | Reviewers: davidxl Reviewed By: davidxl Subscribers: Jim, eraman, hiraditya, haicheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71646
* [LoopUtils] Updated deleteDeadLoop() to handle loop nest.Whitney Tsang2019-12-181-1/+13
| | | | | | | | | Reviewer: kariddi, sanjoy, reames, Meinersbur, bmahjour, etiotto, kbarton Reviewed By: Meinersbur Subscribers: mgorny, hiraditya, llvm-commits Tag: LLVM Differential Revision: https://reviews.llvm.org/D70939
* [ThinLTO] Show preserved symbols in DOT filesevgeny2019-12-184-20/+27
| | | | Differential revision: https://reviews.llvm.org/D71608
* [gicombiner] Import tryCombineIndexedLoadStore()Daniel Sanders2019-12-182-18/+28
| | | | | | | | | | | | | | | | | Summary: Now that arbitrary data is supported, import tryCombineIndexedLoadStore() Depends on D69147 Reviewers: bogner, volkan Reviewed By: volkan Subscribers: hiraditya, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69151
* [AArch64] match fcvtl2 with bitcasted extractSanjay Patel2019-12-182-6/+35
| | | | | | | | | | | | | This should eliminate a regression seen in D63815. If we are FP extending the high half extract of a vector, we should be able to peek through a bitcast sitting between the extract and extend. This replaces tablegen patterns with a more general DAG to DAG override, so we can handle any casted type. Differential Revision: https://reviews.llvm.org/D71515
* [gicombiner] Add support for arbitrary match data being passed from match to ↵Daniel Sanders2019-12-181-14/+12
| | | | | | | | | | | | | | | | | | | | | apply Summary: This is used by the extending_loads combine to tell the apply step which use is the preferred one to fold and the other uses should be re-written to consume. Depends on D69117 Reviewers: volkan, bogner Reviewed By: volkan Subscribers: hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69147
* Revert "[DebugInfo] Correctly handle salvaged casts and split fragments at ISel"stozer2019-12-183-45/+11
| | | | | | Reverted due to build failure on windows bots. This reverts commit bb1b0bc4e57428ce364d3d6c075ff03cb8973462.
* [DebugInfo] Correctly handle salvaged casts and split fragments at ISelstozer2019-12-183-11/+45
| | | | | | | | | | | | | | | Previously, LLVM had no functional way of performing casts inside of a DIExpression(), which made salvaging cast instructions other than Noop casts impossible. This patch enables the salvaging of casts by using the DW_OP_LLVM_convert operator for SExt and Trunc instructions. There is another issue which is exposed by this fix, in which fragment DIExpressions (which are preserved more readily by this patch) for values that must be split across registers in ISel trigger an assertion, as the 'split' fragments extend beyond the bounds of the fragment DIExpression causing an error. This patch also fixes this issue by checking the fragment status of DIExpressions which are to be split, and dropping fragments that are invalid.
* [AArch64] Improve codegen of volatile load/store of i128Victor Campos2019-12-183-14/+69
| | | | | | | | | | | | | | | | Summary: Instead of generating two i64 instructions for each load or store of a volatile i128 value (two LDRs or STRs), now emit a single LDP or STP. Reviewers: labrinea, t.p.northover, efriedma Reviewed By: efriedma Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69559
* [AArch64] Enable clustering memory accesses to fixed stack objectsJay Foad2019-12-184-119/+91
| | | | | | | | | | | | | | | | | | Summary: r347747 added support for clustering mem ops with FI base operands including support for fixed stack objects in shouldClusterFI, but apparently this was never tested. This patch fixes shouldClusterFI to work with scaled as well as unscaled load/store instructions, and fixes the ordering of memory ops in MemOpInfo::operator< to ensure that memory addresses always increase, regardless of which direction the stack grows. Subscribers: MatzeB, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71334
* [NFC][TTI] Add Alignment for isLegalMasked[Gather/Scatter]Anna Welker2019-12-186-25/+38
| | | | | | | Add an extra parameter so alignment can be taken under consideration in gather/scatter legalization. Differential Revision: https://reviews.llvm.org/D71610
* [X86] Add calculation for elements in structures in getting uniform base for ↵Wang, Pengfei2019-12-181-6/+28
| | | | | | | | | | | | | | | the Gather/Scatter intrinsic. Summary: Add calculation for elements in structures in getting uniform base for the Gather/Scatter intrinsic. Reviewers: craig.topper, c-rhodes, RKSimon Subscribers: hiraditya, llvm-commits, annita.zhang, LuoYuanke Tags: #llvm Differential Revision: https://reviews.llvm.org/D71442
* [X86] Add strict fma supportWang, Pengfei2019-12-184-19/+26
| | | | | | | | | | | | Summary: Add strict fma support Reviewers: craig.topper, RKSimon, LiuChen3 Subscribers: hiraditya, llvm-commits, LuoYuanke Tags: #llvm Differential Revision: https://reviews.llvm.org/D71604
* [PowerPC] Add missing legalization for vector BSWAPNemanja Ivanovic2019-12-174-3/+31
| | | | | | | | We somehow missed doing this when we were working on Power9 exploitation. This just adds the missing legalization and cost for producing the vector intrinsics. Differential revision: https://reviews.llvm.org/D70436
* [X86] Manually format some setOperationAction calls to line up arguments to ↵Craig Topper2019-12-171-8/+8
| | | | improve readability. NFC
* [AArch64][GlobalISel]: Fix a crash in GlobalIsel in dealing with 16bit ↵Xiaoqing Wu2019-12-171-1/+2
| | | | | | | | | | | | | | | | uadd.with.overflow. Summary: AArch64 doesn't support uadd.with.overflow.i16 natively. This change adds a legalization rule to convert the 32bit add result to 16bit. This should fix PR43981. Reviewers: arsenm, qcolombet, paquette, aemerson Reviewed By: paquette Subscribers: wdng, rovka, kristof.beyls, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71587
* [FPEnv][LegalizeTypes] Make ScalarizeVecOp_STRICT_FP_ROUND do its own ↵Craig Topper2019-12-171-1/+7
| | | | | | | | | | | | replacements and return SDValue() The caller will assert for nodes with more than 2 results unless we return a null SDValue. I tried to test this by copying an AArch64 test for ScalarizeVecOp_FP_ROUND. While it did hit the assert and this commited fixed that. It also hit a later problem that couldn't be fixed without adding strict FP support to AArch64.
* [AMDGPU] Fixed cost model for packed 16 bit opsStanislav Mekhanoshin2019-12-171-1/+13
| | | | Differential Revision: https://reviews.llvm.org/D71622
* [WebAssembly] Implement SIMD {i8x16,i16x8}.avgr_u instructionsThomas Lively2019-12-171-1/+20
| | | | | | | | | | | | | | | | | Summary: These instructions were added to the spec proposal in https://github.com/WebAssembly/simd/pull/126. Their semantics are equivalent to `(a + b + 1) / 2`. The opcode for the experimental i32x4.dot_i16x8_s is also bumped due to a collision with the i8x16.avgr_u opcode. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71628
* Revert "[ MC ] Match labels to existing fragments even when switching sections."Mitch Phillips2019-12-172-94/+13
| | | | | | | This reverts commit 4272372c571cd33edc77a8844b0a224ad7339138. Caused an MSan buildbot failure. More information available in the patch that introduced the bug: https://reviews.llvm.org/D71368
* [FPEnv][LegalizeTypes][LegalizeDAG][AArch64] Few fixes/improvements for ↵Craig Topper2019-12-174-2/+22
| | | | | | | | | | | | | | | | legalizing fp<->int conversion nodes. This started with adding a test to support get code coverage on ScalarizeVecOp_UnaryOp_StrictFP by copying an existing AArch64 test and using constrained sitofp/uitofp intrinsics. This found 3 separate issues: -ScalarizeVecOp_UnaryOp_StrictFP needs to do its own replacement because the caller can't handle replacing multiple results. -Missing integer promotion support for sitofp/uitofp -Chain result not always assigned in ExpandLegalINT_TO_FP. Committing them together so I can add the test case.
* [LoopFusion] Move instructions from FC0.Latch to FC1.Latch.Whitney Tsang2019-12-172-3/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary:This PR move instructions from FC0.Latch bottom up to the beginning of FC1.Latch as long as they are proven safe. To illustrate why this is beneficial, let's consider the following example: Before Fusion: header1: br header2 header2: br header2, latch1 latch1: br header1, preheader3 preheader3: br header3 header3: br header4 header4: br header4, latch3 latch3: br header3, exit3 After Fusion (before this PR): header1: br header2 header2: br header2, latch1 latch1: br header3 header3: br header4 header4: br header4, latch3 latch3: br header1, exit3 Note that preheader3 is removed during fusion before this PR. Notice that we cannot fuse loop2 with loop4 as there exists block latch1 in between. This PR move instructions from latch1 to beginning of latch3, and remove block latch1. LoopFusion is now able to fuse loop nest recursively. After Fusion (after this PR): header1: br header2 header2: br header3 header3: br header4 header4: br header2, latch3 latch3: br header1, exit3 Reviewer: kbarton, jdoerfert, Meinersbur, dmgreen, fhahn, hfinkel, bmahjour, etiotto Reviewed By: kbarton, Meinersbur Subscribers: hiraditya, llvm-commits Tag: LLVM Differential Revision: https://reviews.llvm.org/D71165
* [AIX] Avoid unset csect assert for functions defined after their use in TOCDavid Tenty2019-12-171-16/+17
| | | | | | | | | | | | | | | | | Summary: If a function is defined after it appears in a TOC expression, we may try to access an unset containing csect when returning a symbol for the expression. Reviewers: Xiangling_L, DiggerLin, jasonliu, hubert.reinterpretcast Reviewed By: hubert.reinterpretcast Subscribers: hubert.reinterpretcast, wuzish, nemanjai, hiraditya, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71125
* AMDGPU/SILoadStoreOptimillzer: Refactor CombineInfo structTom Stellard2019-12-171-241/+216
| | | | | | | | | | | | | | | | | Summary: Modify CombineInfo to only store information about a single instruction. This is a little easier to work with and removes a lot of duplicate initialization code. Reviewers: arsenm, nhaehnle Reviewed By: arsenm, nhaehnle Subscribers: merge_guards_bot, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71045
* [IR] Use a reference in a range-based forMark de Wever2019-12-172-19/+19
| | | | | | | | This avoids unneeded copies when using a range-based for loops. This avoids new warnings due to D68912 adds -Wrange-loop-analysis to -Wall. Differential Revision: https://reviews.llvm.org/D70870
* Recommit "[DebugInfo] Refactored macro related generation,Sourabh Singh Tomar2019-12-183-19/+14
| | | | | | | | | | | | | | | | | | added a test case for macinfo.dwo emission." This was reverted in caa412090666c10f854322cdc701c1cbf8ed726e, since it was causing an assertion failure on Windows bots. This revision is revised to fix that. Original commit message - [DebugInfo] Refactored macro related generation, added a test case for macinfo.dwo emission. Reviewers: dblaikie, aprantl, jini.susan.george Tags: #debug-info #llvm Differential Revision: https://reviews.llvm.org/D71008
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