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* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-073-166/+224
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Simplify FastISel's constructor by giving it a FunctionLoweringInfoDan Gohman2010-07-075-118/+46
| | | | | | | | | instance, rather than pointers to all of FunctionLoweringInfo's members. This eliminates an NDEBUG ABI sensitivity. llvm-svn: 107789
* Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This willDan Gohman2010-07-075-148/+4
| | | | | | allow target-specific fast-isel code to make use of it directly. llvm-svn: 107787
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-0728-94/+137
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* add some triple for minix, patch by Kees van Reeuwijk from PR7582Chris Lattner2010-07-073-3/+6
| | | | llvm-svn: 107785
* Move CallingConvLower.cpp out of the SelectionDAG directory.Dan Gohman2010-07-073-1/+1
| | | | llvm-svn: 107781
* Fix more places assuming subregisters have live intervalsJakob Stoklund Olesen2010-07-071-1/+6
| | | | llvm-svn: 107780
* Add a getFirstNonPHI utility function.Dan Gohman2010-07-071-0/+7
| | | | llvm-svn: 107778
* Minore code simplification.Dan Gohman2010-07-071-17/+15
| | | | llvm-svn: 107777
* Remove interprocedural-basic-aa and associated code. The AliasAnalysisDan Gohman2010-07-073-183/+58
| | | | | | | | | | | interface needs implementations to be consistent, so any code which wants to support different semantics must use a different interface. It's not currently worthwhile to add a new interface for this new concept. Document that AliasAnalysis doesn't support cross-function queries. llvm-svn: 107776
* conditionalize by CallInst::ArgOffsetGabor Greif2010-07-071-2/+2
| | | | llvm-svn: 107767
* Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"Duncan Sands2010-07-071-1/+1
| | | | | | | | | | | | | builds to "Release". The default build is unchanged (optimization on, assertions on), however it is now called Release+Asserts. The intent is that future LLVM releases released via llvm.org will be Release builds in the new sense, i.e. will have assertions disabled (currently they have assertions enabled, for a more than 20% slowdown). This will bring them in line with MacOS releases, which ship with assertions disabled. It also means that "Release" now means the same things in make and cmake builds: cmake already disables assertions for "Release" builds AFAICS. llvm-svn: 107758
* Add AVX SSE4.2 instructionsBruno Cardoso Lopes2010-07-071-114/+179
| | | | llvm-svn: 107752
* Use only one multiclass to pinsrq instructionsBruno Cardoso Lopes2010-07-072-38/+20
| | | | llvm-svn: 107750
* Now that almost all SSE4.1 AVX instructions are added, move code around to ↵Bruno Cardoso Lopes2010-07-072-361/+374
| | | | | | more appropriate sections. No functionality changes llvm-svn: 107749
* Add AVX SSE4.1 insertps, ptest and movntdqa instructionsBruno Cardoso Lopes2010-07-071-18/+39
| | | | llvm-svn: 107747
* Add AVX SSE4.1 extractps and pinsr instructionsBruno Cardoso Lopes2010-07-071-35/+67
| | | | llvm-svn: 107746
* Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.Jakob Stoklund Olesen2010-07-077-9/+136
| | | | | | Buildbot breakage. llvm-svn: 107744
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | llvm-svn: 107743
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. llvm-svn: 107742
* Add AVX SSE4.1 Extract Integer instructionsBruno Cardoso Lopes2010-07-071-0/+11
| | | | llvm-svn: 107740
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-062-2/+9
| | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. llvm-svn: 107734
* Remove references to INSERT_SUBREG after de-SSAJakob Stoklund Olesen2010-07-067-136/+9
| | | | llvm-svn: 107732
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Accept RIP-relative symbols with 'i' constraint, andDale Johannesen2010-07-062-2/+3
| | | | | | | print the (%rip) only if the 'a' modifier is present. PR 7528. llvm-svn: 107727
* Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.Jakob Stoklund Olesen2010-07-063-2/+35
| | | | | | | | | INSERT_SUBREG will now only appear in SSA machine instructions. Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant since partial redef COPY instructions appear. llvm-svn: 107726
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. llvm-svn: 107725
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+17
| | | | llvm-svn: 107723
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+15
| | | | llvm-svn: 107720
* Fix comment from previous patchBruno Cardoso Lopes2010-07-061-1/+1
| | | | llvm-svn: 107717
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-064-10/+61
| | | | | | Update VEX encoding to support those new instructions llvm-svn: 107715
* CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman2010-07-066-11/+11
| | | | | | SelectBasicBlock doesn't needs its BasicBlock argument. llvm-svn: 107712
* Propagate debug loc.Devang Patel2010-07-0619-50/+60
| | | | llvm-svn: 107710
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-063-7/+13
| | | | llvm-svn: 107701
* One more case assuming that subregs have live ranges.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | llvm-svn: 107700
* Fix buildbot breakage where a def is missing.Jakob Stoklund Olesen2010-07-061-0/+2
| | | | llvm-svn: 107698
* Add fixme.Devang Patel2010-07-061-0/+1
| | | | llvm-svn: 107697
* Be more forgiving when calculating alias interference for physreg coalescing.Jakob Stoklund Olesen2010-07-063-105/+59
| | | | | | | | | | | | It is OK for an alias live range to overlap if there is a copy to or from the physical register. CoalescerPair can work out if the copy is coalescable independently of the alias. This means that we can join with the actual destination interval instead of using the getOrigDstReg() hack. It is no longer necessary to merge clobber ranges into subregisters. llvm-svn: 107695
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-0614-212/+275
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Fix to 80-col.Eric Christopher2010-07-061-21/+21
| | | | llvm-svn: 107684
* Fix PR7545 crash.Devang Patel2010-07-061-3/+3
| | | | llvm-svn: 107678
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* tighten up this code.Chris Lattner2010-07-061-12/+7
| | | | llvm-svn: 107670
* Revert r107655.Dan Gohman2010-07-0613-269/+209
| | | | llvm-svn: 107668
* Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperandsDan Gohman2010-07-061-0/+35
| | | | | | which do not depend on SelectionDAG. llvm-svn: 107666
* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Fix a major regression on COFF targets introduced by r103267: 'discardable' ↵Anton Korobeynikov2010-07-061-1/+1
| | | | | | | | section means that it is used only during the program load and can be discarded afterwards. This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc'). llvm-svn: 107658
* Add some more TODO comments.Dan Gohman2010-07-061-0/+6
| | | | llvm-svn: 107657
* Add a comment.Dan Gohman2010-07-061-1/+2
| | | | llvm-svn: 107656
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-0613-209/+269
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
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