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* Remove the block from the LoopInfo, rather than just the Loop.Dan Gohman2009-06-271-1/+1
| | | | | | | LoopInfo will handle removing it from the Loop, as well as updating its own tables. llvm-svn: 74398
* Teach LoopSimplify how to merge multiple loop exits into a single exit,Dan Gohman2009-06-272-1/+76
| | | | | | | | | | | | | | | | when one of them can be converted to a trivial icmp and conditional branch. This addresses what is essentially a phase ordering problem. SimplifyCFG knows how to do this transformation, but it doesn't do so if the primary block has any instructions in it other than an icmp and a branch. In the given testcase, the block contains other instructions, however they are loop-invariant and can be hoisted. SimplifyCFG doesn't have LoopInfo though, so it can't hoist them. And, it's important that the blocks be merged before LoopRotation, as it doesn't support multiple-exit loops. llvm-svn: 74396
* More minor code simplifications.Dan Gohman2009-06-271-14/+9
| | | | llvm-svn: 74395
* Eliminate a layer of indirection in LoopInfo and MachineLoopInfo.Dan Gohman2009-06-272-2/+2
| | | | llvm-svn: 74394
* Convert ScalarEvolution to use BumpPtrAllocator and FoldingSet, insteadDan Gohman2009-06-271-141/+222
| | | | | | of a team of individual allocations and a team of std::maps. llvm-svn: 74393
* Change SCEVExpander to use an IRBuilder to emit instructions.Dan Gohman2009-06-271-72/+70
| | | | llvm-svn: 74391
* Simplify a bitAnton Korobeynikov2009-06-276-80/+70
| | | | llvm-svn: 74385
* ARM refactoring. Step 2: split RegisterInfoAnton Korobeynikov2009-06-279-694/+1075
| | | | llvm-svn: 74384
* Add ThumbInstrInfo.cpp to the CMake makefilesDouglas Gregor2009-06-271-0/+1
| | | | llvm-svn: 74382
* remove a bunch of fixmes (old checking code) and commonize all theChris Lattner2009-06-271-87/+29
| | | | | | target-specific operand printing functionality. Yay. llvm-svn: 74379
* pull @GOT, @GOTOFF, @GOTPCREL handling into isel from the asmprinter.Chris Lattner2009-06-272-40/+23
| | | | llvm-svn: 74378
* simplify some code and eliminate the symbolicAddressesAreRIPRel() predicate.Chris Lattner2009-06-273-19/+4
| | | | llvm-svn: 74377
* When a value is used multiple times within a single PHI, instructionsDan Gohman2009-06-271-3/+15
| | | | | | | | inserted to replace that value must dominate all of of the basic blocks associated with the uses of the value in the PHI, not just one of them. llvm-svn: 74376
* fix clang/test/CodeGenObjC/try.m, a basereg doesn't mean no global anymore.Chris Lattner2009-06-271-5/+3
| | | | llvm-svn: 74375
* fix a bunch of failures in the X86-64 JIT by tolerating RIP asChris Lattner2009-06-271-3/+5
| | | | | | a base register. We just ignore it for now. llvm-svn: 74374
* factor some logic out into a helper function, allow remat of loads from constantChris Lattner2009-06-271-4/+25
| | | | | | globals. This implements remat-constant.ll even without aggressive-remat. llvm-svn: 74373
* Reimplement rip-relative addressing in the X86-64 backend. The newChris Lattner2009-06-279-165/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. llvm-svn: 74372
* When doing remat, don't consider uses of non-allocatable physregs. Patch Chris Lattner2009-06-271-0/+4
| | | | | | by Evan. llvm-svn: 74370
* Renaming for consistency.Evan Cheng2009-06-275-115/+120
| | | | llvm-svn: 74368
* Fix PR4466 by making fastisel set operand flags correctly.Chris Lattner2009-06-272-7/+14
| | | | llvm-svn: 74366
* fix a typo that GCC should have caught that causes crashes with -view-*-dagsChris Lattner2009-06-271-1/+1
| | | | llvm-svn: 74364
* Remove outdated comment.David Goodwin2009-06-261-4/+0
| | | | llvm-svn: 74357
* When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has ↵David Goodwin2009-06-261-0/+2
| | | | | | a narrow version and eor(i) does not. llvm-svn: 74355
* Incorporate the insertion point into the key of SCEVExpander's CSE map.Dan Gohman2009-06-262-135/+62
| | | | | | | | | | | | | | This helps it avoid reusing an instruction that doesn't dominate all of the users, in cases where the original instruction was inserted before all of the users were known. This may result in redundant expansions of sub-expressions that depend on loop-unpredictable values in some cases, however this isn't very common, and it primarily impacts IndVarSimplify, so GVN can be expected to clean these up. This eliminates the need for IndVarSimplify's FixUsesBeforeDefs, which fixes several bugs. llvm-svn: 74352
* Remove unused routines.Devang Patel2009-06-261-41/+0
| | | | llvm-svn: 74351
* Add feature flags for AVX and FMA and fix some SSE4A feature flagDavid Greene2009-06-264-3/+38
| | | | | | initialization problems. llvm-svn: 74350
* Fix ScalarEvolution::getAddRecExpr's code which canonicalized theDan Gohman2009-06-261-2/+23
| | | | | | | | nesting order of nested AddRec expressions to skip the transformation if it would introduce an AddRec with operands not loop-invariant with respect to its loop. llvm-svn: 74343
* Fix SCEVAddRecExpr::isLoopInvariant to test if all of its operandsDan Gohman2009-06-261-5/+15
| | | | | | are loop invariant, not just the start operand. llvm-svn: 74338
* Add x86 support for 'n' inline asm modifier. This will be handled target ↵Evan Cheng2009-06-261-0/+11
| | | | | | independently as part of MC work. llvm-svn: 74336
* simplify printing of MO_ExternalSymbol in a non-pcrel context.Chris Lattner2009-06-261-23/+11
| | | | llvm-svn: 74334
* Privatize some data.Owen Anderson2009-06-261-2/+2
| | | | llvm-svn: 74332
* Constify this value.Owen Anderson2009-06-261-3/+2
| | | | llvm-svn: 74330
* Split thumb-related stuff into separate classes.Anton Korobeynikov2009-06-2612-349/+596
| | | | | | Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo llvm-svn: 74329
* add %rip to the GR64 register class. Lets avoid allocating it to anything ↵Chris Lattner2009-06-262-3/+6
| | | | | | though! :) llvm-svn: 74328
* Move all the TLS processing logic into isel, don't do it in asmprinter at all.Chris Lattner2009-06-263-59/+123
| | | | llvm-svn: 74327
* make sure to propagate operand flags in SelectTLSADDRAddr properly.Chris Lattner2009-06-261-1/+2
| | | | llvm-svn: 74326
* fix a really subtle bug in the cross section of aliases and TLS:Chris Lattner2009-06-261-9/+3
| | | | | | | | | | | the SelectionDAG::getGlobalAddress function properly looks through aliases to determine thread-localness, but then passes the GV* down to GlobalAddressSDNode::GlobalAddressSDNode which does not. Instead of passing down isTarget, just pass down the predetermined node opcode. This fixes some assertions with out of tree changes I'm working on. llvm-svn: 74325
* Thumb-2 has CLZ.David Goodwin2009-06-261-1/+1
| | | | llvm-svn: 74322
* Use "adcs/sbcs" only when the carry-out is live, otherwise use "adc/sbc".David Goodwin2009-06-261-3/+3
| | | | llvm-svn: 74321
* Get rid of these cache variables, which are a holdover from the days whenOwen Anderson2009-06-261-41/+28
| | | | | | we had multiple type planes and these lookups were expensive. llvm-svn: 74319
* Make this const.Owen Anderson2009-06-261-1/+1
| | | | llvm-svn: 74317
* minor cleanup/framework changes.Chris Lattner2009-06-261-3/+11
| | | | llvm-svn: 74316
* Privatize some variables.Owen Anderson2009-06-261-5/+4
| | | | llvm-svn: 74315
* move magic for PIC constantpool references from asmprinter to isel.Chris Lattner2009-06-262-23/+44
| | | | llvm-svn: 74313
* implement DOTGraphTraits<SelectionDAG*>::getNodeLabel in terms ofChris Lattner2009-06-261-138/+5
| | | | | | SDNode::print_details to eliminate a ton of near-duplicate code. llvm-svn: 74311
* use jump table operand flags in asm printer instead of "magic predicates"Chris Lattner2009-06-261-6/+18
| | | | llvm-svn: 74310
* Use atomic operations for accessing this global counter.Owen Anderson2009-06-261-3/+6
| | | | llvm-svn: 74294
* ADC used to implement adde should use "adcs" opcode instead of "adc". David Goodwin2009-06-261-2/+2
| | | | llvm-svn: 74293
* Get rid of unnecessary global variables.Owen Anderson2009-06-262-7/+2
| | | | llvm-svn: 74291
* Currently there is a pattern for the thumb-2 MOV 16-bit immediate ↵David Goodwin2009-06-261-3/+8
| | | | | | | | instruction. That instruction cannot write the flags so it should use T2I instead of T2sI. Also, added a pattern for the thumb-2 MOV of shifted immediate since that can encode immediates not encodable by the 16-bit immediate. llvm-svn: 74288
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