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* [CGP] use subtract or subtract-of-cmps for result of memcmp expansionSanjay Patel2017-07-311-6/+18
| | | | | | | | | | | | | | | | | | | | | | As noted in the code comment, transforming this in the other direction might require a separate transform here in CGP given the block-at-a-time DAG constraint. Besides that theoretical motivation, there are 2 practical motivations for the subtract-of-cmps form: 1. The codegen for both x86 and PPC is better for this IR (though PPC could be better still). There is discussion about canonicalizing IR to the select form ( http://lists.llvm.org/pipermail/llvm-dev/2017-July/114885.html ), so we probably need to add DAG transforms for those patterns anyway, but this improves the memcmp output without waiting for that step. 2. If we allow vector-sized chunks for the load and compare, x86 is better prepared to convert that to optimal code when using subtract-of-cmps, so another prerequisite patch is avoided if we choose to enable that. Differential Revision: https://reviews.llvm.org/D34904 llvm-svn: 309597
* [DWARF] Added verification check for tags in accelerator tables. This patch ↵Spyridoula Gravani2017-07-312-7/+23
| | | | | | | | verifies that the atom tag is actually the same with the tag of the DIE that we retrieve from the table. Differential Revision: https://reviews.llvm.org/D35963 llvm-svn: 309596
* [IPSCCP] Guard a user of getInitializer with hasDefinitiveInitializerDavid Majnemer2017-07-311-1/+2
| | | | | | | We are not allowed to reason about an initializer value without first consulting hasDefinitiveInitializer. llvm-svn: 309594
* [AVX-512] Remove patterns that select vmovdqu8/16 for unmasked loads. Prefer ↵Craig Topper2017-07-311-11/+18
| | | | | | | | | | | | | | vmovdqa64/vmovdqu64 instead. These were taking priority over the aligned load instructions since there is no vmovda8/16. I don't think there is really a difference between aligned and unaligned on newer cpus so I don't think it matters which instructions we use. But with this change we reduce the size of the isel table a little and we allow the aligned information to pass through to the evex->vec pass and produce the same output has avx/avx2 in some cases. I also generally dislike patterns rooted in a bitcast which these were. Differential Revision: https://reviews.llvm.org/D35977 llvm-svn: 309589
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-07-311-7/+7
| | | | llvm-svn: 309584
* Fix typo in comment.Simon Pilgrim2017-07-311-1/+1
| | | | llvm-svn: 309583
* [GISel]: Support Widening G_ICMP's destination operand.Aditya Nandakumar2017-07-313-15/+55
| | | | | | | | | Updated AArch64 to widen destination to s32. https://reviews.llvm.org/D35737 Reviewed by Tim llvm-svn: 309579
* Do not recombine FMA when that is not needed.Amaury Sechet2017-07-311-4/+16
| | | | | | | | | | | | Summary: As per title. This creates useless recombines. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33848 llvm-svn: 309578
* Exclude more unused functions from release build.Florian Hahn2017-07-311-0/+4
| | | | llvm-svn: 309576
* Extend ifndef to printDebugLoc.Florian Hahn2017-07-311-1/+1
| | | | | | GCC7 did not warn about that, but Clang does. llvm-svn: 309573
* Extend ifdefs to more unused helper functions.Florian Hahn2017-07-312-5/+5
| | | | | | This fixes a buildbot failure with -Werror introduced by r309553 llvm-svn: 309572
* [DebugInfo] Don't overwrite DWARFUnit fields if the CU DIE doesn't have them.Benjamin Kramer2017-07-311-2/+6
| | | | | | | | | | DIEs are lazily deserialized so it's possible that the DWO CU is created before the DIE is parsed. DWO shares .debug_addr and .debug_ranges with the object file so overwriting the offset with 0 will make the CU unusable. No test case because I couldn't get clang to emit a non-zero range base. llvm-svn: 309570
* [SLP] Initial rework for min/max horizontal reduction vectorization, NFC.Alexey Bataev2017-07-312-88/+227
| | | | | | | | | | | | Summary: All getReductionCost() functions are renamed to getArithmeticReductionCost() + added basic infrastructure to handle non-binary reduction operations. Reviewers: spatel, mzolotukhin, Ayal, mkuper, gilr, hfinkel Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D29402 llvm-svn: 309566
* [Cost] Rename getReductionCost() to getArithmeticReductionCost(), NFC.Alexey Bataev2017-07-315-11/+14
| | | | llvm-svn: 309563
* [SelectionDAG][mips] Fix PR33883Simon Dardis2017-07-311-15/+24
| | | | | | | | | | | | | | | PR33883 shows that calls to intrinsic functions should not have their vector arguments or returns subject to ABI changes required by the target. This resolves PR33883. Thanks to Alex Crichton for reporting the issue! Reviewers: zoran.jovanovic, atanasyan Differential Revision: https://reviews.llvm.org/D35765 llvm-svn: 309561
* [LV] Avoid redundant operations manipulating masksAyal Zaks2017-07-312-36/+39
| | | | | | | | | | | | | | | | The Loop Vectorizer generates redundant operations when manipulating masks: AND with true, OR with false, compare equal to true. Instead of relying on a subsequent pass to clean them up, this patch avoids generating them. Use null (no-mask) to represent all-one full masks, instead of a constant all-one vector, following the convention of masked gathers and scatters. Preparing for a follow-up VPlan patch in which these mask manipulating operations are modeled using recipes. Differential Revision: https://reviews.llvm.org/D35725 llvm-svn: 309558
* [llvm-dlltool] Write correct weak externalsMartin Storsjo2017-07-311-8/+5
| | | | | | | | | | | | | Previously, the created object files for the import library were broken. Write the symbol table before the string table. Simplify the code by using a separate variable Prefix instead of duplicating a few lines. Also update the coff-weak-exports to actually check that the generated weak symbols can be found as intended. Differential Revision: https://reviews.llvm.org/D36065 llvm-svn: 309555
* Guard print() functions only used by dump() functions.Florian Hahn2017-07-3110-7/+23
| | | | | | | | | | | | | | | | | | | Summary: Since r293359, most dump() function are only defined when `!defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)` holds. print() functions only used by dump() functions are now unused in release builds, generating lots of warnings. This patch only defines some print() functions if they are used. Reviewers: MatzeB Reviewed By: MatzeB Subscribers: arsenm, mzolotukhin, nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D35949 llvm-svn: 309553
* [Support/GlobPattern] - Do not crash when pattern has characters with int ↵George Rimar2017-07-311-7/+10
| | | | | | | | | | | | | | | value < 0. Found it during work on LLD, it would crash on following linker script: SECTIONS { .foo : { *("*®") } } That happens because ® has int value -82. And chars are used as array index in code, and are signed by default. Differential revision: https://reviews.llvm.org/D35891 llvm-svn: 309549
* [LoopInterchange] Do not interchange loops with function calls.Florian Hahn2017-07-311-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Without any information about the called function, we cannot be sure that it is safe to interchange loops which contain function calls. For example there could be dependences that prevent interchanging between accesses in the called function and the loops. Even functions without any parameters could cause problems, as they could access memory using global pointers. For now, I think it is only safe to interchange loops with calls marked as readnone. With this patch, the LLVM test suite passes with `-O3 -mllvm -enable-loopinterchange` and LoopInterchangeProfitability::isProfitable returning true for all loops. check-llvm and check-clang also pass when bootstrapped in a similar fashion, although only 3 loops got interchanged. Reviewers: karthikthecool, blitz.opensource, hfinkel, mcrosier, mkuper Reviewed By: mcrosier Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D35489 llvm-svn: 309547
* [X86][AVX512] Add masked MOVS[S|D] patternsGuy Blank2017-07-311-0/+16
| | | | | | | | | | | Added patterns to recognize AND 1 on the mask of a scalar masked move is not needed since only the lower bit is relevant for the instruction. Differential Revision: https://reviews.llvm.org/D35897 llvm-svn: 309546
* [PowerPC] Change method names; NFCHiroshi Inoue2017-07-311-24/+25
| | | | | | | | Changed method names based on the discussion in https://reviews.llvm.org/D34986: getInt64 -> selectI64Imm, getInt64Count -> selectI64ImmInstrCount. llvm-svn: 309541
* [X86] Add pattern to use bzhi for 64-bit 'and' with a mask when there is a ↵Craig Topper2017-07-311-0/+4
| | | | | | | | load involved. We already had a pattern without load, but with a load we were falling back to a regular 'and' due to pattern complexity priority. llvm-svn: 309535
* DebugInfo: Fix r309526, ensure resetting base address selection entries are usedDavid Blaikie2017-07-311-0/+6
| | | | | | | Missed the resetting base address selections when going from a base address version to zero base address for non-base-addressed entries. llvm-svn: 309529
* DebugInfo: Use base address selection entries in debug_ranges to reduce ↵David Blaikie2017-07-301-10/+35
| | | | | | | | | | | | | | | | | | | | relocations (from comments in the test) Group ranges in a range list that apply to the same section and use a base address selection entry to reduce the number of relocations to one reloc per section per range list. DWARF5 debug_rnglist will be more efficient than this in terms of relocations, but it's still better than one reloc per entry in a range list. This is an object/executable size tradeoff - shrinking objects, but growing the linked executable. In one large binary tested, total object size (not just debug info) shrank by 16%, entirely relocation entries. Linked executable grew by 4%. This was with compressed debug info in the objects, uncompressed in the linked executable. Without compression in the objects, the win would be smaller (the growth of debug_ranges itself would be more significant). llvm-svn: 309526
* DebugInfo: Fix for CU index usage in 309507David Blaikie2017-07-301-1/+3
| | | | | | Not sure quite how I failed so clearly to test this, but anyway. llvm-svn: 309514
* [x86][inline-asm][ms-compat] legalize the use of "jc/jz short <op>"Coby Tayree2017-07-301-1/+2
| | | | | | | | | MS ignores the keyword "short" when used after a jc/jz instruction, LLVM ought to do the same. Test: D35893 Differential Revision: https://reviews.llvm.org/D35892 llvm-svn: 309509
* DebugInfo: Use DWP cu_index to speed up symbolizing (as intended)David Blaikie2017-07-302-3/+26
| | | | | | | | | | | I was a bit lazy when I first implemented this & skipped the index lookup - obviously for large files this becomes pretty crucial, so here we go, do the index lookup. Speeds up large DWP symbolizing by... lots. (20m -> 20s, actually, maybe more in a release build (that was a release build without index lookup, compared to a debug/non-release build with the index usage)) llvm-svn: 309507
* [X86] Add addsub intrinsics to the intrinsic lowering table so we have a ↵Craig Topper2017-07-302-48/+24
| | | | | | single set of isel patterns. llvm-svn: 309502
* Refactor the build{Module|Function}SimplificationPipeline to expose ↵Dehao Chen2017-07-301-18/+19
| | | | | | | | | | | | | | | | optimization phase. Summary: This is in preparation of https://reviews.llvm.org/D36052 Reviewers: chandlerc, davidxl, tejohnson Reviewed By: chandlerc Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D36053 llvm-svn: 309500
* DebugInfo: Provide option for explicitly specifying the name of the DWP fileDavid Blaikie2017-07-302-13/+19
| | | | | | | | | | | | | | | | If you've archived the DWP file somewhere it's probably useful to be able to just tell llvm-symbolizer where it is when you're symbolizing stack traces from the binary. This only provides a mechanism for specifying a single DWP file, good if you're symbolizing a program with a single DWP file, but it's likely if the program is dynamically linked that you might have a DWP for each dynamic library - in which case this feature won't help (at least as it's surfaced in llvm-symbolizer for now) - in theory it could be extended to specify a collection of DWP files that could all be consulted for split CU hash resolution. llvm-svn: 309498
* Migrate PGOMemOptSizeOpt to use new OptimizationRemarkEmitter PassSam Elliott2017-07-302-13/+25
| | | | | | | | | | | | | | | | | Summary: Fixes PR33790. This patch still needs a yaml-style test, which I shall write tomorrow Reviewers: anemet Reviewed By: anemet Subscribers: anemet, llvm-commits Differential Revision: https://reviews.llvm.org/D35981 llvm-svn: 309497
* [AArch64] Tie source and destination operands for AESMC/AESIMC. Florian Hahn2017-07-293-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Most CPUs implementing AES fusion require instruction pairs of the form AESE Vn, _ AESMC Vn, Vn and AESD Vn, _ AESIMC Vn, Vn The constraint is added to AES(I)MC instructions which use the result of an AES(E|D) instruction by using AES(I)MCTrr pseudo instructions, which constraint source and destination registers to be the same. A nice side effect of this change is that now all possible pairs are scheduled back-to-back on the exynos-m1 for the misched-fusion-aes.ll test case. I had to update aes_load_store. The version I added initially was very reduced and with the new constraint, AESE/AESMC could not be scheduled back-to-back. I updated the test to be more realistic and still expose the same scheduling problem as the initial test case. Reviewers: t.p.northover, rengolin, evandro, kristof.beyls, silviu.baranga Reviewed By: t.p.northover, evandro Subscribers: aemerson, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D35299 llvm-svn: 309495
* [AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.Florian Hahn2017-07-291-1/+3
| | | | | | | | | | | | | | | | | | Summary: This change gives a 0.25% speedup on execution time, a 0.82% improvement in benchmark scores and a 0.20% increase in binary size on a Cortex-A53. These numbers are the geomean results on a wide range of benchmarks from the test-suite and a range of proprietary suites. Reviewers: t.p.northover, aadg, silviu.baranga, mcrosier, rengolin Reviewed By: rengolin Subscribers: grimar, davide, aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35568 llvm-svn: 309494
* MC: simplify internal function call parameterSaleem Abdulrasool2017-07-291-30/+26
| | | | | | | | | | Rather than passing along most of the parameters, pass a reference to the MCDWARFrameInfo instead. This makes it easier to pass additional information about the frame to the checks. We need to keep the extra constructor for the Key around to allow the construction of the null and tombstone keys. NFC. llvm-svn: 309493
* MC: account for the return column in the CIE keySaleem Abdulrasool2017-07-291-8/+11
| | | | | | | | If the return column is different, we cannot coalesce the CIE across the FDEs. Add that to the key calculation. This ensures that we emit a separate CIE. llvm-svn: 309492
* [SelectionDAG][X86] CombineBT - more aggressively determine demanded bitsSimon Pilgrim2017-07-292-12/+20
| | | | | | | | | | | | This patch is in 2 parts: 1 - replace combineBT's use of SimplifyDemandedBits (hasOneUse only) with SelectionDAG::GetDemandedBits to more aggressively determine the lower bits used by BT. 2 - update SelectionDAG::GetDemandedBits to support ANY_EXTEND - if the demanded bits are only in the non-extended portion, then peek through and demand from the source value and then ANY_EXTEND that if we found a match. Differential Revision: https://reviews.llvm.org/D35896 llvm-svn: 309486
* [SCEV] Change an early exit to an assert; NFCSanjoy Das2017-07-291-2/+2
| | | | llvm-svn: 309480
* Refine the PGOOpt and SamplePGOSupport handling.Dehao Chen2017-07-291-7/+12
| | | | | | | | | | | | | | | | | | | Summary: Now that SamplePGOSupport is part of PGOOpt, there are several places that need tweaking: 1. AddDiscriminator pass should *not* be invoked at ThinLTOBackend (as it's already invoked in the PreLink phase) 2. addPGOInstrPasses should only be invoked when either ProfileGenFile or ProfileUseFile is non-empty. 3. SampleProfileLoaderPass should only be invoked when SampleProfileFile is non-empty. 4. PGOIndirectCallPromotion should only be invoked in ProfileUse phase, or in ThinLTOBackend of SamplePGO. Reviewers: chandlerc, tejohnson, davidxl Reviewed By: chandlerc Subscribers: sanjoy, mehdi_amini, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D36040 llvm-svn: 309478
* AMDGPU: Remove deadcode from AMDGPUInstPrinterTom Stellard2017-07-293-28/+1
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D36034 llvm-svn: 309477
* AMDGPU: Move INDIRECT_BASE_ADDR definition out of common filesTom Stellard2017-07-293-3/+1
| | | | | | | | | | | | | | Summary: This is only used by R600. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D35926 llvm-svn: 309476
* [MachineOutliner] NFC: Change IsTailCall to a call class + frame classJessica Paquette2017-07-295-197/+271
| | | | | | | | | | | | | | | | | | | | | This commit - Removes IsTailCall and replaces it with a target-defined unsigned - Refactors getOutliningCallOverhead and getOutliningFrameOverhead so that they don't use IsTailCall - Adds a call class + frame class classification to OutlinedFunction and Candidate respectively This accomplishes a couple things. Firstly, we don't need the notion of *tail call* in the general outlining algorithm. Secondly, we now can have different "outlining classes" for each candidate within a set of candidates. This will make it easy to add new ways to outline sequences for certain targets and dynamically choose an appropriate cost model for a sequence depending on the context that that sequence lives in. Ultimately, this should get us closer to being able to do something like, say avoid saving the link register when outlining AArch64 instructions. llvm-svn: 309475
* AMDGPU: Make areMemAccessesTriviallyDisjoint more aware of segment flatMatt Arsenault2017-07-292-1/+9
| | | | | | | Checking the encoding is insufficient since now there can be global or scratch instructions. llvm-svn: 309472
* AMDGPU: Teach isLegalAddressingMode about global_* instructionsMatt Arsenault2017-07-292-16/+25
| | | | | | | | Also refine the flat check to respect flat-for-global feature, and constant fallback should check global handling, not specifically MUBUF. llvm-svn: 309471
* AMDGPU: Start selecting global instructionsMatt Arsenault2017-07-293-7/+107
| | | | llvm-svn: 309470
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-298-216/+279
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309469
* [llvm] Update MachOObjectFile::exports interfaceAlexander Shaposhnikov2017-07-291-3/+2
| | | | | | | | | | This diff removes the second argument of the method MachOObjectFile::exports. In all in-tree uses this argument is equal to "this" and without this argument the interface seems to be cleaner. Test plan: make check-all llvm-svn: 309462
* Remove the unused offset field from LiveDebugValues (NFC)Adrian Prantl2017-07-281-16/+3
| | | | | | | Followup to r309426. rdar://problem/33580047 llvm-svn: 309455
* Remove the unused offset field from LiveDebugVariables (NFC)Adrian Prantl2017-07-281-17/+14
| | | | | | | Followup to r309426. rdar://problem/33580047 llvm-svn: 309451
* Remove the unused offset from DBG_VALUE (NFC)Adrian Prantl2017-07-287-23/+23
| | | | | | | Followup to r309426. rdar://problem/33580047 llvm-svn: 309450
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