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* [Hexagon] Lowering of V60/HVX vector typesKrzysztof Parzyszek2015-11-263-89/+469
| | | | llvm-svn: 254168
* [X86] Strengthen more type constraints to reduce isel table size.Craig Topper2015-11-261-12/+24
| | | | llvm-svn: 254167
* [Hexagon] Hexagon V60 HVX intrinsic defintionsKrzysztof Parzyszek2015-11-265-1/+911
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 254165
* [mips][ias] Range check uimm5 operands and fix several bugs this revealed.Daniel Sanders2015-11-265-77/+127
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
* [AArch64] Add ARMv8.2-A new AT instruction variantsOliver Stannard2015-11-263-1/+32
| | | | | | | | | | | ARMv8.2-A adds new variants of the "at" (address translate) system instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These are a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15018 llvm-svn: 254159
* ARM: address WOA unsigned division overflow crashMartell Malone2015-11-262-20/+19
| | | | | | | | | Building on r253865 the crash is not limited to signed overflows. Disable custom handling of unsigned 32-bit and 64-bit integer divide. Add test cases for both 32-bit and 64-bit unsigned integer overflow. llvm-svn: 254158
* [AArch64] Add ARMv8.2-A UAO PSTATE bitOliver Stannard2015-11-265-3/+17
| | | | | | | | | | | | | ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR instructions to behave the same as LDR/STR with respect to execute-only pages at higher privilege levels. New variants of the MSR/MRS instructions are added to allow reading and writing this bit. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15020 llvm-svn: 254157
* [AArch64] Add ARMv8.2-A persistent memory instructionOliver Stannard2015-11-263-3/+18
| | | | | | | | | | | ARMv8.2-A adds the "dc cvap" instruction, which is a system instruction that cleans caches to the point of persistence (for systems that have persistent memory). It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15016 llvm-svn: 254156
* [AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 registerOliver Stannard2015-11-262-0/+2
| | | | | | | | | | ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part of ARMv8.2-A, so no additional subtarget features are required. Differential Revision: http://reviews.llvm.org/D15017 llvm-svn: 254155
* [AArch64] Add subtarget features for ARMv8.2-AOliver Stannard2015-11-264-5/+20
| | | | | | | | | | | | | | This adds subtarget features for ARMv8.2-A, which builds on (and requires the features from) ARMv8.1-A. Most assembler-visible features of ARMv8.2-A are system instructions, and are all required parts of the architecture, so just depend on the HasV8_2aOps subtarget feature. There is also one large, optional feature, which adds 16-bit floating point versions of all existing floating-point instructions (VFP and SIMD), this is represented by the FeatureFullFP16 subtarget feature. Differential Revision: http://reviews.llvm.org/D15013 llvm-svn: 254154
* [SimplifyLibCalls] Don't depend on a called function having a name, it might ↵Benjamin Kramer2015-11-261-11/+8
| | | | | | | | be an indirect call. Fixes the crasher in PR25651 and related crashers using the same pattern. llvm-svn: 254145
* [X86] Strengthen more type constraints to reduce isel table size.Craig Topper2015-11-261-21/+33
| | | | llvm-svn: 254142
* X86-FMA3: Improved/enabled the memory folding optimization for scalar loadsVyacheslav Klochkov2015-11-262-13/+17
| | | | | | | | | | generated for _mm_losd_s{s,d}() intrinsics and used in scalar FMAs generated for FMA intrinsics _mm_f{madd,msub,nmadd,nmsub}_s{s,d}(). Reviewer: David Kreitzer Differential Revision: http://reviews.llvm.org/D14762 llvm-svn: 254140
* [X86] Strengthen the type constraints on X86psadbw and X86dbpsadbw to reduce ↵Craig Topper2015-11-261-2/+6
| | | | | | some of the type checks in the isel matching tables. llvm-svn: 254139
* [Hexagon] HVX vector register classes and more isel patternsKrzysztof Parzyszek2015-11-265-80/+204
| | | | llvm-svn: 254132
* AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsicTom Stellard2015-11-265-1/+28
| | | | | | | | | | | | | | Summary: This returns a pointer to the dispatch packet, which can be used to load information about the kernel dispach. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D14898 llvm-svn: 254116
* [PGO] Implement ValueProfiling Closure interfaces for runtime value profile dataXinliang David Li2015-11-251-3/+119
| | | | | | | | | | | | | | | | This is one of the many steps to commonize value profiling support between profile runtime and compiler/llvm tools. After this change, profiler runtime now can share the same C APIs to do VP serialization/deseriazation with LLVM host tools (and produces value data in identical format between indexed and raw profile). It is not yet enabled in profiler runtime yet. Also added a unit test case to test runtime profile data serialization/deserialization interfaces implemented using common closure code. llvm-svn: 254110
* [safestack] Fix alignment of dynamic allocas.Evgeniy Stepanov2015-11-251-1/+1
| | | | | | Fixes PR25588. llvm-svn: 254109
* [WebAssembly] Fix inline asm support for i64 operands.Dan Gohman2015-11-251-1/+5
| | | | llvm-svn: 254106
* [WebAssembly] Fold setne and seteq comparisons into selects.Dan Gohman2015-11-252-0/+28
| | | | llvm-svn: 254104
* [libFuzzer] add a flag -exact_artifact_pathKostya Serebryany2015-11-255-0/+12
| | | | llvm-svn: 254100
* [Hexagon] Treat transfers of FP immediates are pseudo instructionsKrzysztof Parzyszek2015-11-252-5/+19
| | | | | | | | This is a temporary fix to address ICE on 2005-10-21-longlonggtu.ll. The proper fix will be to use A2_tfrsi, but it will need more work to teach all users of A2_tfrsi to also expect a floating-point operand. llvm-svn: 254099
* [WebAssembly] Add some comments. NFC.Dan Gohman2015-11-251-0/+5
| | | | llvm-svn: 254096
* AMDGPU/SI: select S_ABS_I32 when possible (v2)Marek Olsak2015-11-253-0/+37
| | | | | | | | | | v2: added more tests, moved the SALU->VALU conversion to a separate function It looks like it's not possible to get subregisters in the S_ABS lowering code, and I don't feel like guessing without testing what the correct code would look like. llvm-svn: 254095
* [WebAssembly] Fix WebAssembly register numbering for registers added late.Dan Gohman2015-11-252-0/+9
| | | | | | | | | If virtual registers are created late, mappings to WebAssembly registers need to be added explicitly. This patch adds a function to do so and teaches WebAssemblyPeephole to use it. This fixes an out-of-bounds access on the WARegs vector. llvm-svn: 254094
* [SCCP] More informative message if we don't know how to handle a terminator.Davide Italiano2015-11-251-1/+1
| | | | llvm-svn: 254093
* AMDGPU: Check feature attributes in SIMachineFunctionInfoMatt Arsenault2015-11-252-9/+134
| | | | llvm-svn: 254091
* Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the defaultKrzysztof Parzyszek2015-11-252-32/+59
| | | | llvm-svn: 254089
* AMDGPU: Make v2i64/v2f64 legal types.Matt Arsenault2015-11-253-3/+60
| | | | | | | They can be loaded and stored, so count them as legal. This is mostly to fix a number of common cases for load/store merging. llvm-svn: 254086
* Expose isXxxConstant() functions from SelectionDAGNodes.h (NFC)Artyom Skrobov2015-11-258-198/+112
| | | | | | | | | | | | | | Summary: Many target lowerings copy-paste the code to test SDValues for known constants. This code can instead be shared in SelectionDAG.cpp, and reused in the targets. Reviewers: MatzeB, andreadb, tstellarAMD Subscribers: arsenm, jyknight, llvm-commits Differential Revision: http://reviews.llvm.org/D14945 llvm-svn: 254085
* [WebAssembly] Use a physical register to describe ARGUMENT liveness.Dan Gohman2015-11-2510-38/+66
| | | | | | | | | | Instead of trying to move ARGUMENT instructions back up to the top after they've been scheduled or sunk down, use a fake physical register to create a liveness constraint that prevents ARGUMENT instructions from moving down in the first place. This is still not entirely ideal, however it is more robust than letting them move and moving them back. llvm-svn: 254084
* [PGO] Regroup functions in better order (NFC)Xinliang David Li2015-11-251-93/+96
| | | | llvm-svn: 254080
* [WebAssembly] Clean up several FIXME comments.Dan Gohman2015-11-256-10/+12
| | | | llvm-svn: 254079
* [WebAssembly] Support for register stackifying with load and store instructions.Dan Gohman2015-11-259-29/+314
| | | | llvm-svn: 254076
* [WebAssembly] Codegen support for ISD::ExternalSymbolDan Gohman2015-11-254-2/+26
| | | | llvm-svn: 254075
* [WebAssembly] Add 'final' to some classes. NFC.Dan Gohman2015-11-252-2/+2
| | | | llvm-svn: 254073
* [WebAssembly] Whitespace consistency. NFC.Dan Gohman2015-11-252-2/+0
| | | | llvm-svn: 254071
* fix typo; NFCSanjay Patel2015-11-251-1/+1
| | | | llvm-svn: 254069
* [PowerPC] Don't generate mfocrf on the e500mcHal Finkel2015-11-251-1/+1
| | | | | | | | | The e500mc does not actually support the mfocrf instruction; update the processor definitions to reflect that fact. Patch by Tom Rix (with some test-case cleanup by me). llvm-svn: 254064
* Fix some places where we were assuming that memory type had been legalizedEric Christopher2015-11-252-3/+2
| | | | | | | | | | to a simple type when lowering a truncating store of a vector type. In this case for an EVT we'll return Expand as we should in all of the cases anyhow. The testcase triggered at the one in VectorLegalizer::LegalizeOp, inspection found the rest. llvm-svn: 254061
* AVX-512: Fixed a bug in VPERMT2* intrinsic.Elena Demikhovsky2015-11-253-51/+138
| | | | | | | | | It was wrong order of operands (from intrinsic to DAG node). I added more strict type specification for instruction selection. Differential Revision: http://reviews.llvm.org/D14942 llvm-svn: 254059
* [PGO] Convert InstrProfRecord based serialization methods to use common C ↵Xinliang David Li2015-11-251-35/+97
| | | | | | | | | | | | | | | | methods 1. Convert serialization methods using InstrProfRecord as source into C (impl) interfaces using Closure. 2. Reimplement InstrProfRecord serialization method to use new C interface as dummy wrapper. Now it is ready to implement wrapper for runtime value profile data. (The new code need better source location -- but not changed in this patch to minimize diffs. ) llvm-svn: 254057
* [PGO] convert a subset of C++ interfaces into C (for sharing) (NFC)Xinliang David Li2015-11-251-28/+10
| | | | llvm-svn: 254056
* Move member functions closer to others of the same class (NFC)Xinliang David Li2015-11-251-14/+16
| | | | llvm-svn: 254055
* AsmParser: Make the code for parsing unnamed aliases more closely resemble ↵Peter Collingbourne2015-11-251-18/+27
| | | | | | | | | | that for unnamed globals. This fixes parsing of forward references to unnamed aliases. While here, remove an unnecessary isa check. llvm-svn: 254054
* [OperandBundles] Extract duplicated code into a helper function, NFCSanjoy Das2015-11-252-10/+2
| | | | llvm-svn: 254047
* [InstCombine] Don't drop operand bundlesSanjoy Das2015-11-251-3/+10
| | | | | | | | | | Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14857 llvm-svn: 254046
* Fix function naming (NFC)Xinliang David Li2015-11-251-2/+2
| | | | llvm-svn: 254045
* Revert r253528: "[X86] Enable shrink-wrapping by default."Hans Wennborg2015-11-251-5/+0
| | | | | | | | | This caused PR25607 and also caused Chromium to crash on start-up. (Also had to update test/CodeGen/X86/avx-splat.ll, which was committed after shrink wrapping was enabled.) llvm-svn: 254044
* Fix an asan error where NumElements > 32 for at least one case inKaelyn Takata2015-11-251-2/+3
| | | | | | test/CodeGen/X86/avg.ll. llvm-svn: 254043
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