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* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-076-41/+29
| | | | llvm-svn: 176648
* Hexagon: Handle i8, i16 and i1 Var Args.Jyotsna Verma2013-03-071-0/+10
| | | | llvm-svn: 176647
* Simplify code. No functionality change.Jakub Staszak2013-03-071-3/+3
| | | | llvm-svn: 176646
* Change NULL to 0.Jakub Staszak2013-03-071-8/+8
| | | | llvm-svn: 176642
* ArrayRef ca accept one element. Simplify code a little bit, also it matches nowJakub Staszak2013-03-071-3/+5
| | | | | | coding in the other places of the file. llvm-svn: 176641
* pre-RA-sched debug-only fixAndrew Trick2013-03-071-2/+4
| | | | llvm-svn: 176638
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-074-0/+28
| | | | llvm-svn: 176637
* pre-RA-sched assertion fix. This bug was exposed by r176037.Andrew Trick2013-03-071-3/+0
| | | | | | | | | | | | | rdar:13370002 [pre-RA-sched] assertion: released too many times I tracked this down to an earlier hack that is no longer applicable and interfered with normal scheduler logic. With the changes in r176037, it was causing an instruction to be scheduled multiple times. I have an external test case that I tried hard to reduce and failed. I can't even reproduce with llc. llvm-svn: 176636
* X86: Fold EXTRACT_SUBVECTORs of a BUILD_VECTOR into a smaller BUILD_VECTOR.Benjamin Kramer2013-03-071-0/+5
| | | | | | | | | | That can usually be lowered efficiently and is common in sandybridge code. It would be nice to do this in DAGCombiner but we can't insert arbitrary BUILD_VECTORs this late. Fixes PR15462. llvm-svn: 176634
* Fixed a crash when cloning a function into a function withPekka Jaaskelainen2013-03-071-3/+6
| | | | | | | different size argument list and without attributes in the arguments. llvm-svn: 176632
* R600/SI: rework input interpolation v2Christian Konig2013-03-0712-321/+46
| | | | | | | | v2: update CMakeLists.txt as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176626
* R600/SI: remove SI_vs_load_buffer_indexChristian Konig2013-03-072-15/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176625
* R600/SI: remove SGPR address space v2Christian Konig2013-03-075-70/+21
| | | | | | | | v2: fix R600 regressions Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176624
* R600/SI: add proper formal parameter handling for SIChristian Konig2013-03-077-22/+163
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
* R600/SI: remove shader type intrinsicChristian Konig2013-03-076-18/+18
| | | | | | | | Just encode the type as target specific attribute. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176622
* R600/SI: switch types of SGPRs to v*i8Christian Konig2013-03-074-11/+24
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176621
* R600/SI: fix unused variable warningChristian Konig2013-03-071-1/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176620
* Switch from a version 4.2/4.4 switch to a four-byte version string to be putNick Lewycky2013-03-071-23/+25
| | | | | | | | | into the actual gcov file. Instead of using the bottom 4 bytes as the function identifier, use a counter. This makes the identifier numbers stable across multiple runs. llvm-svn: 176616
* No need to go through int64 and APInt when generating a new constant.Nadav Rotem2013-03-071-3/+3
| | | | llvm-svn: 176615
* SDAG: Handle scalarizing an extend of a <1 x iN> vector.Jim Grosbach2013-03-072-0/+21
| | | | | | | | | Just scalarize the element and rebuild a vector of the result type from that. rdar://13281568 llvm-svn: 176614
* Debug Info: store the files and directories for each compile unit.Manman Ren2013-03-079-33/+60
| | | | | | | | | | | | | | We now emit a line table for each compile unit. To reduce the prologue size of each line table, the files and directories used by each compile unit are stored in std::map<unsigned, std::vector< > > instead of std::vector< >. The prologue for a lto'ed image can be as big as 93K. Duplicating 93K for each compile unit causes a huge increase of debug info. With this patch, each prologue will only emit the files required by the compile unit. rdar://problem/13342023 llvm-svn: 176605
* ArrayRef has a OneElt constructor. Beautify the code.Nadav Rotem2013-03-071-2/+1
| | | | llvm-svn: 176604
* Switch from std::vector to ArrayRef. Speedup FoldBitCast by 5x.Nadav Rotem2013-03-071-3/+3
| | | | llvm-svn: 176602
* SimplifyCFG fix for volatile load/store.Andrew Trick2013-03-071-2/+4
| | | | | | | | | | | | | Fixes rdar:13349374. Volatile loads and stores need to be preserved even if the language standard says they are undefined. "volatile" in this context means "get out of the way compiler, let my platform handle it". Additionally, this is the only way I know of with llvm to write to the first page (when hardware allows) without dropping to assembly. llvm-svn: 176599
* Fix two remaining issue after fixing PR15355 when CMOV is not availableMichael Liao2013-03-071-6/+22
| | | | | | | | | | | - Phi nodes should be replaced/updated after lowering CMOV into branch because 'mainMBB' updating operand in Phi node is changed. - Add EFLAGS in livein before lowering the 2nd CMOV. It's necessary as we will reuse the EFLAGS generated before the 1st lowered CMOV, which won't clobber EFLAGS. However, we need explicitly specify that. - '-attr=-cmov' test case are added. llvm-svn: 176598
* [mips] Custom-legalize BR_JT.Akira Hatanaka2013-03-062-1/+33
| | | | | | In N64-static, GOT address is needed to compute the branch address. llvm-svn: 176580
* Generalize my previous fix for -print-options.Andrew Trick2013-03-061-1/+1
| | | | | | | Always print options that differ from their implicit default. At least for simple option types. llvm-svn: 176572
* Give -loop-vectorize an explicit default.Andrew Trick2013-03-061-1/+1
| | | | | | This way, clang -mllvm -print-options shows that the driver is overriding it. llvm-svn: 176569
* Memory Dependence Analysis (not mem-dep test) take advantage of ↵Shuxin Yang2013-03-062-4/+19
| | | | | | | | | | | | | | | | "invariant.load" metadata. The "invariant.load" metadata indicates the memory unit being accessed is immutable. A load annotated with this metadata can be moved across any store. As I am not sure if it is legal to move such loads across barrier/fence, this change dose not allow such transformation. rdar://11311484 Thank Arnold for code review. llvm-svn: 176562
* InstCombine: Don't shrink allocas when combining with a bitcast.Jim Grosbach2013-03-061-0/+6
| | | | | | | | | | When considering folding a bitcast of an alloca into the alloca itself, make sure we don't shrink the amount of memory being allocated, or things rapidly go sideways. rdar://13324424 llvm-svn: 176547
* Fix PR15355Michael Liao2013-03-061-102/+182
| | | | | | | | | | | | | - Clear 'mayStore' flag when loading from the atomic variable before the spin loop - Clear kill flag from one use to multiple use in registers forming the address to that atomic variable - don't use a physical register as live-in register in BB (neither entry nor landing pad.) by copying it into virtual register (patch by Cameron Zwarich) llvm-svn: 176538
* Use dyn_cast instead of isa && cast. No functionality change.Jakub Staszak2013-03-061-4/+4
| | | | llvm-svn: 176537
* [mips] Remove android calling convention.Akira Hatanaka2013-03-054-19/+1
| | | | | | | This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. llvm-svn: 176530
* [mips] Fix MipsCC::analyzeReturn so that, in soft-float mode, fp128 getsAkira Hatanaka2013-03-052-40/+55
| | | | | | returned in registers $2 and $4. llvm-svn: 176527
* [mips] Fix MipsTargetLowering::LowerCallResult and LowerReturn to correctlyAkira Hatanaka2013-03-052-15/+74
| | | | | | handle fp128 returns. llvm-svn: 176523
* [mips] Fix MipsTargetLowering::LowerCall to pass fp128 arguments in floatingAkira Hatanaka2013-03-052-6/+15
| | | | | | point registers. llvm-svn: 176521
* [mips] Correct handling of fp128 (long double) formals and read long doubleAkira Hatanaka2013-03-052-9/+79
| | | | | | parameters from floating point registers if target is mips64 hard float. llvm-svn: 176520
* Add more functions to the TLI.Meador Inge2013-03-051-9/+212
| | | | | | | | | | | This patch adds many more functions to the target library information. All of the functions being added were discovered while doing the migration of the simplify-libcalls attribute annotation functionality to the functionattrs pass. As a part of that work the attribute annotation logic will query TLI to determine if a function should be annotated or not. Signed-off-by: Meador Inge <meadori@codesourcery.com> llvm-svn: 176514
* reverting patch 176508.Jyotsna Verma2013-03-054-28/+0
| | | | llvm-svn: 176513
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-054-0/+28
| | | | llvm-svn: 176508
* R600: Do not predicate vector opVincent Lejeune2013-03-051-0/+2
| | | | llvm-svn: 176507
* Hexagon: Expand addc, adde, subc and sube.Jyotsna Verma2013-03-051-0/+23
| | | | llvm-svn: 176505
* Update cmake build.Benjamin Kramer2013-03-051-0/+1
| | | | llvm-svn: 176501
* Hexagon: Use MO operand flags to mark constant extended instructions.Jyotsna Verma2013-03-053-471/+43
| | | | llvm-svn: 176500
* Hexagon: Add encoding bits to the TFR64 instructions.Jyotsna Verma2013-03-051-20/+46
| | | | | | Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. llvm-svn: 176499
* R600: initial scheduler codeVincent Lejeune2013-03-053-1/+624
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently it only tries to expose more parallelism for ALU instructions (this also makes the distribution of GPR channels more uniform and increases the chances of ALU instructions to be packed together in a single VLIW group). Also it tries to reduce clause switching by grouping instruction of the same kind (ALU/FETCH/CF) together. Vincent Lejeune: - Support for VLIW4 Slot assignement - Recomputation of ScheduleDAG to get more parallelism opportunities Tom Stellard: - Fix assertion failure when trying to determine an instruction's slot based on its destination register's class - Fix some compiler warnings Vincent Lejeune: [v2] - Remove recomputation of ScheduleDAG (will be provided in a later patch) - Improve estimation of an ALU clause size so that heuristic does not emit cf instructions at the wrong position. - Make schedule heuristic smarter using SUnit Depth - Take constant read limitations into account Vincent Lejeune: [v3] - Fix some uninitialized values in ConstPair - Add asserts to ensure an ALU slot is always populated llvm-svn: 176498
* R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.Vincent Lejeune2013-03-055-228/+11
| | | | | | | Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case and taking them in account for scheduling is difficult for no real benefit. llvm-svn: 176488
* R600: Turn BUILD_VECTOR into Reg_SequenceVincent Lejeune2013-03-052-1/+29
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 176487
* R600: CONST_ADDRESS node is not marked as mayLoad anymoreVincent Lejeune2013-03-051-1/+1
| | | | | | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> mayLoad complexify scheduling and does not bring any usefull info as the location is not writeable at all. llvm-svn: 176486
* R600: Use MUL_IEEE for trig/fdiv intrinsicVincent Lejeune2013-03-051-4/+4
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 176485
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