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* [LoopUnroll] Make LoopPeeling respect the AllowPeeling preference.Chad Rosier2018-04-061-10/+14
| | | | | | | | The SimpleLoopUnrollPass isn't suppose to perform loop peeling. Differential Revision: https://reviews.llvm.org/D45334 llvm-svn: 329395
* DWARFVerifier: validate information in name index entriesPavel Labath2018-04-062-3/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch add checks to verify that the information in the name index entries is consistent with the debug_info section. Specifically, we check that entries point to valid DIEs, and their names, tags, and compile units match the information in the debug_info sections. These checks are only run if the previous checks did not find any errors in the name index headers. Attempting to proceed with the checks anyway would likely produce a lot of spurious errors and the verification code would need to be very careful to avoid crashing. I also add a couple of more checks to the abbreviation-validation code to verify that some attributes are always present (an index without a DW_IDX_die_offset attribute is fairly useless). The entry verification works only on indexes without any type units - I haven't attempted to extend it to type units, as we don't even have a DWARF v5-compatible type unit generator at the moment. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45323 llvm-svn: 329392
* [X86][SandyBridge] Add (V)DPPS memory fold latenciesSimon Pilgrim2018-04-061-0/+14
| | | | | | Noticed this during D44654 llvm-svn: 329389
* [X86][SandyBridge] SBWriteResPair +5cy Memory FoldsSimon Pilgrim2018-04-061-6/+6
| | | | | | | | | | | | As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
* Tweak an assert message in the verifierHans Wennborg2018-04-061-1/+1
| | | | llvm-svn: 329387
* [X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI.Simon Pilgrim2018-04-061-2/+2
| | | | llvm-svn: 329386
* EntryExitInstrumenter: Handle musttail callsHans Wennborg2018-04-061-5/+15
| | | | | | | | Inserting instrumentation between a musttail call and ret instruction would create invalid IR. Instead, treat musttail calls as function exits. llvm-svn: 329385
* [NFC] Add missing end of line symbolsMax Kazantsev2018-04-061-3/+3
| | | | llvm-svn: 329383
* [MIR] Add support for MachineFrameInfo::LocalFrameSizeFrancis Visoiu Mistrih2018-04-062-0/+2
| | | | | | | | | | MFI.LocalFrameSize was not serialized. It is usually set from LocalStackSlotAllocation, so if that pass doesn't run it is impossible do deduce it from the stack objects. Until now, this information was lost. llvm-svn: 329382
* [debug_loc] Fix typo in DWARFExpression constructorPavel Labath2018-04-062-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The positions of the DwarfVersion and AddressSize arguments were reversed, which caused parsing for dwarf opcodes which contained address-size-dependent operands (such as DW_OP_addr). Amusingly enough, none of the address-size asserts fired, as dwarf version was always 4, which is a valid address size. I ran into this when constructing weird inputs for the DWARF verifier. I I add a test case as hand-written dwarf -- I am not sure how to trigger this differently, as having a DW_OP_addr inside a location list is a fairly non-standard thing to do. Fixing this error exposed a bug in the debug_loc.dwo parser, which was always being constructed with an address size of 0. I fix that as well by following the pattern in the non-dwo parser of picking up the address size from the first compile unit (which is technically not correct, but probably good enough in practice). Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45324 llvm-svn: 329381
* [NFC] Loosen restriction on preheader to fix buildbotMax Kazantsev2018-04-061-5/+5
| | | | llvm-svn: 329379
* [PowerPC] allow D-form VSX load/store when accessing FrameIndex without offset Hiroshi Inoue2018-04-061-8/+16
| | | | | | | | | | VSX D-form load/store instructions of POWER9 require the offset be a multiple of 16 and a helper`isOffsetMultipleOf` is used to check this. So far, the helper handles FrameIndex + offset case, but not handling FrameIndex without offset case. Due to this, we are missing opportunities to exploit D-form instructions when accessing an object or array allocated on stack. For example, x-form store (stxvx) is used for int a[4] = {0}; instead of d-form store (stxv). For larger arrays, D-form instruction is not used when accessing the first 16-byte. Using D-form instructions reduces register pressure as well as instructions. Differential Revision: https://reviews.llvm.org/D45079 llvm-svn: 329377
* [LLVM-C] Audit Inline Assembly APIs for ConsistencyRobert Widmann2018-04-061-0/+32
| | | | | | | | | | | | | | | | | | Summary: - Add a missing getter for module-level inline assembly - Add a missing append function for module-level inline assembly - Deprecate LLVMSetModuleInlineAsm and replace it with LLVMSetModuleInlineAsm2 which takes an explicit length parameter - Deprecate LLVMConstInlineAsm and replace it with LLVMGetInlineAsm, a function that allows passing a dialect and is not mis-classified as a constant operation Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45346 llvm-svn: 329369
* Fix lld-x86_64-darwin13 build fails.Manoj Gupta2018-04-051-4/+4
| | | | | | | Use double braces in std::array initialization to keep Darwin builders happy. llvm-svn: 329363
* [InstCombine] FP: Z - (X - Y) --> Z + (Y - X)Sanjay Patel2018-04-051-2/+11
| | | | | | | | | | | | This restores what was lost with rL73243 but without re-introducing the bug that was present in the old code. Note that we already have these transforms if the ops are marked 'fast' (and I assume that's happening somewhere in the code added with rL170471), but we clearly don't need all of 'fast' for these transforms. llvm-svn: 329362
* Attempt to fix Mips breakages.Manoj Gupta2018-04-051-7/+8
| | | | | | | | | | | | | | Summary: Replace ArrayRefs by actual std::array objects so that there are no dangling references. Reviewers: rsmith, gkistanova Subscribers: sdardis, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D45338 llvm-svn: 329359
* [X86] Separate CDQ and CDQE in the scheduler model.Craig Topper2018-04-055-20/+10
| | | | | | According to Agner's data, CDQE is closer to CWDE. llvm-svn: 329354
* [IR] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-054-6/+6
| | | | | | | | | | | | | | r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer D44363 for a list of all the required patches. llvm-svn: 329353
* [X86] Add MOVZPQILo2PQIrr to the Sandy Bridge scheduler modelCraig Topper2018-04-051-1/+1
| | | | llvm-svn: 329351
* [InstCombine] nsz: -(X - Y) --> Y - XSanjay Patel2018-04-051-4/+11
| | | | | | This restores part of the fold that was removed with rL73243 (PR4374). llvm-svn: 329350
* [X86] Add LEAVE instruction to the scheduler models using the same data as ↵Craig Topper2018-04-055-22/+16
| | | | | | | | | | LEAVE64. Make LEAVE/LEAVE64 more correct on Sandy Bridge. This is the 32-bit mode version of LEAVE64. It should be at least somewhat similar to LEAVE64. The Sandy Bridge version was missing a load port use. llvm-svn: 329347
* [DWARF v5][NFC]: Refactor DebugRnglists to prepare for the support of the ↵Wolfgang Pieb2018-04-052-99/+128
| | | | | | | | | | | | DW_AT_ranges attribute in conjunction with .debug_rnglists. Reviewers: JDevlieghere Differential Revision: https://reviews.llvm.org/D45307 llvm-svn: 329345
* AMDGPU/Metadata: Always report a fixed number of hidden argumentsKonstantin Zhuravlyov2018-04-051-8/+12
| | | | | | | | | | Currently it is 6. If the "feature" was not used, report dummy hidden argument. Otherwise it does not match the kernarg size reported in the kernel header. Differential Revision: https://reviews.llvm.org/D45129 llvm-svn: 329341
* [X86] Remove some InstRWs for plain store instructions on Sandy Bridge.Craig Topper2018-04-055-39/+5
| | | | | | We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329339
* [RuntimeDyld][PowerPC] Use global entry points for calls between sections.Lang Hames2018-04-051-9/+13
| | | | | | | | | | | | | | | | | | Functions in different objects may use different TOCs, so calls between such functions should use the global entry point of the callee which updates the TOC pointer. This should fix a bug that the Numba developers encountered (see https://github.com/numba/numba/issues/2451). Patch by Olexa Bilaniuk. Thanks Olexa! No RuntimeDyld checker test case yet as I am not familiar enough with how RuntimeDyldELF fixes up call-sites, but I do not want to hold up landing this. I will continue to work on it and see if I can rope some powerpc experts in. llvm-svn: 329335
* [Bitcode] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-053-4/+4
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: pcc, mehdi_amini, dexonsmith Reviewed By: dexonsmith Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45132 llvm-svn: 329334
* [InstCombine] Properly change GEP type when reassociating loop invariant GEP ↵Daniel Neilson2018-04-051-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chains Summary: This is a fix to PR37005. Essentially, rL328539 ([InstCombine] reassociate loop invariant GEP chains to enable LICM) contains a bug whereby it will convert: %src = getelementptr inbounds i8, i8* %base, <2 x i64> %val %res = getelementptr inbounds i8, <2 x i8*> %src, i64 %val2 into: %src = getelementptr inbounds i8, i8* %base, i64 %val2 %res = getelementptr inbounds i8, <2 x i8*> %src, <2 x i64> %val By swapping the index operands if the GEPs are in a loop, and %val is loop variant while %val2 is loop invariant. This fix recreates new GEP instructions if the index operand swap would result in the type of %src changing from vector to scalar, or vice versa. Reviewers: sebpop, spatel Reviewed By: sebpop Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45287 llvm-svn: 329331
* [X86] Synchronize the SchedRW on some EVEX instructions with their VEX ↵Craig Topper2018-04-051-67/+82
| | | | | | | | equivalents. Mostly vector load, store, and move instructions. llvm-svn: 329330
* [ARM] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-054-18/+18
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: t.p.northover, RKSimon, MatzeB, bkramer Reviewed By: bkramer Subscribers: javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D44855 llvm-svn: 329329
* [X86] Disassembler support for having an ADSIZE prefix affect instructions ↵Craig Topper2018-04-051-0/+3
| | | | | | | | with 0xf2 and 0xf3 prefixes. Needed to support umonitor from D45253. llvm-svn: 329327
* [InstCombine] use pattern matchers for fsub --> fadd foldsSanjay Patel2018-04-051-4/+9
| | | | | | This allows folding for vectors with undef elements. llvm-svn: 329316
* [WebAssembly] Allow for the creation of user-defined custom sectionsSam Clegg2018-04-052-2/+65
| | | | | | | | | | | | | This patch adds a way for users to create their own custom sections to be added to wasm files. At the LLVM IR layer, they are defined through the "wasm.custom_sections" named metadata. The expected use case for this is bindings generators such as wasm-bindgen. Patch by Dan Gohman Differential Revision: https://reviews.llvm.org/D45297 llvm-svn: 329315
* [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with ↵Craig Topper2018-04-051-1/+1
| | | | | | VEXTRACTI128 which uses WriteShuffle256. llvm-svn: 329310
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to describe properties of the hardware retire control unit. Tablegen class RetireControlUnit has been added for this purpose (see TargetSchedule.td). A RetireControlUnit specifies the size of the reorder buffer, as well as the maximum number of opcodes that can be retired every cycle. A zero (or negative) value for the reorder buffer size means: "the size is unknown". If the size is unknown, then llvm-mca defaults it to the value of field SchedMachineModel::MicroOpBufferSize. A zero or negative number of opcodes retired per cycle means: "there is no restriction on the number of instructions that can be retired every cycle". Models can optionally specify an instance of RetireControlUnit. There can only be up-to one RetireControlUnit definition per scheduling model. Information related to the RCU (RetireControlUnit) is stored in (two new fields of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp). This patch fixes PR36661. Differential Revision: https://reviews.llvm.org/D45259 llvm-svn: 329304
* [PowerPC] fix assertion failure due to missing instruction in ↵Hiroshi Inoue2018-04-051-3/+3
| | | | | | | | P9InstrResources.td This patch adds L(W|H|B)ZXTLS_32 instructions introduced by https://reviews.llvm.org/rL327635 in P9InstrResources.td. llvm-svn: 329299
* Re-land r329273: [Plugins] Add a slim plugin API to work together with the ↵Philip Pfaffe2018-04-052-0/+51
| | | | | | | | | new PM Fix unittest: Do not link LLVM into the test plugin. Additionally, remove an unrelated change that slipped in in r329273. llvm-svn: 329293
* [Testing/Support]: Better matching of Error failure statesPavel Labath2018-04-051-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The existing Failed() matcher only allowed asserting that the operation failed, but it was not possible to verify any details of the returned error. This patch adds two new matchers, which make this possible: - Failed<InfoT>() verifies that the operation failed with a single error of a given type. - Failed<InfoT>(M) additionally check that the contained error info object is matched by the nested matcher M. To make these work, I've changed the implementation of the ErrorHolder class. Now, instead of just storing the string representation of the Error, it fetches the ErrorInfo objects and stores then as a list of shared pointers. This way, ErrorHolder remains copyable, while still retaining the full information contained in the Error object. In case the Error object contains two or more errors, the new matchers will fail to match, instead of trying to match all (or any) of the individual ErrorInfo objects. This seemed to be the most sensible behavior for when one wants to match exact error details, but I could be convinced otherwise... Reviewers: zturner, lhames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44925 llvm-svn: 329288
* ARM: Do not spill CSR to stack on entry to noreturn functionsTim Northover2018-04-053-0/+31
| | | | | | | | | | | | | | A noreturn nounwind function can be expected to never return in any way, and by never returning it will also never have to restore any callee-saved registers for its caller. This makes it possible to skip spills of those registers during function entry, saving some stack space and time in the process. This is rather useful for embedded targets with limited stack space. Should fix PR9970. Patch by myeisha (pmb). llvm-svn: 329287
* [Hexagon] Remove default values from lambda parametersKrzysztof Parzyszek2018-04-051-23/+23
| | | | llvm-svn: 329286
* [DAGCombine] Revert r329160Sam Parker2018-04-051-26/+0
| | | | | | Again, broke the big endian stage 2 builders. llvm-svn: 329283
* [InstCombine] cleanup; NFCSanjay Patel2018-04-051-15/+12
| | | | llvm-svn: 329282
* [SchedModel] Complete models shouldn't match against itineraries when they ↵Simon Pilgrim2018-04-054-4/+4
| | | | | | | | | | | | don't use them (PR35639) For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp This patch causes problems for a number of models that had been incorrectly flagged as complete. Differential Revision: https://reviews.llvm.org/D43235 llvm-svn: 329280
* Revert "[Plugins] Add a slim plugin API to work together with the new PM"Philip Pfaffe2018-04-052-51/+0
| | | | | | This reverts commit ecf3ba1ab45edb1b0fadce716a7facf50dca4fbb/r329273. llvm-svn: 329276
* [Plugins] Add a slim plugin API to work together with the new PMPhilip Pfaffe2018-04-052-0/+51
| | | | | | | | | | | | | | | | | | | | | | Summary: Add a new plugin API. This closes the gap between pass registration and out-of-tree passes for the new PassManager. Unlike with the existing API, interaction with a plugin is always initiated from the tools perspective. I.e., when a plugin is loaded, it resolves and calls a well-known symbol `llvmGetPassPluginInfo` to obtain details about the plugin. The fundamental motivation is to get rid of as many global constructors as possible. The API exposed by the plugin info is kept intentionally minimal. Reviewers: chandlerc Reviewed By: chandlerc Subscribers: bollu, grosser, lksbhm, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D35258 llvm-svn: 329273
* [LoopInterchange] Add stats counter for number of interchanged loops.Florian Hahn2018-04-051-0/+4
| | | | | | | | | | Reviewers: samparker, karthikthecool, blitz.opensource Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D45209 llvm-svn: 329269
* allow custom OptBisect classes set to LLVMContextFedor Sergeev2018-04-053-6/+25
| | | | | | | | | | | | | | | | | | | | | This patch introduces a way to set custom OptPassGate instances to LLVMContext. A new instance field OptBisector and a new method setOptBisect() are added to the LLVMContext classes. These changes allow to set a custom OptBisect class that can make its own decisions on skipping optional passes. Another important feature of this change is ability to set different instances of OptPassGate to different LLVMContexts. So the different contexts can be used independently in several compiling threads of one process. One unit test is added. Patch by Yevgeny Rouban. Reviewers: andrew.w.kaylor, fedor.sergeev, vsk, dberlin, Eugene.Zelenko, reames, skatkov Reviewed By: andrew.w.kaylor, fedor.sergeev Differential Revision: https://reviews.llvm.org/D44464 llvm-svn: 329267
* [LoopInterchange] Preserve LoopInfo after interchanging.Florian Hahn2018-04-051-13/+72
| | | | | | | | | | | | | | LoopInterchange relies on LoopInfo being up-to-date, so we should preserve it after interchanging. This patch updates restructureLoops to move the BBs of the interchanged loops to the right place. Reviewers: davide, efriedma, karthikthecool, mcrosier Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45278 llvm-svn: 329264
* [MIR-Canon] Fixing warnings in Non-assert builds.Puyan Lotfi2018-04-051-2/+2
| | | | llvm-svn: 329258
* [X86] Revert r329251-329254Craig Topper2018-04-057-88/+107
| | | | | | | | | | | | | It's failing on the bots and I'm not sure why. This reverts: [X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents. [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256. [X86] Remove some InstRWs for plain store instructions on Sandy Bridge. [X86] Auto-generate complete checks. NFC llvm-svn: 329256
* [X86] Synchronize the SchedRW on some EVEX instructions with their VEX ↵Craig Topper2018-04-051-67/+82
| | | | | | | | equivalents. Mostly vector load, store, and move instructions. llvm-svn: 329254
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