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* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-1512-1610/+83
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover2013-02-151-12/+29
| | | | | | | | In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. llvm-svn: 175257
* Simplify the 'operator<' for the attribute object.Bill Wendling2013-02-151-15/+13
| | | | llvm-svn: 175252
* BBVectorize: Cap the number of candidate pairs in each instruction groupHal Finkel2013-02-151-1/+9
| | | | | | | | | | | | | | | | | | | | | | | For some basic blocks, it is possible to generate many candidate pairs for relatively few pairable instructions. When many (tens of thousands) of these pairs are generated for a single instruction group, the time taken to generate and rank the different vectorization plans can become quite large. As a result, we now cap the number of candidate pairs within each instruction group. This is done by closing out the group once the threshold is reached (set now at 3000 pairs). Although this will limit the overall compile-time impact, this may not be the best way to achieve this result. It might be better, for example, to prune excessive candidate pairs after the fact the prevent the generation of short, but highly-connected groups. We can experiment with this in the future. This change reduces the overall compile-time slowdown of the csa.ll test case in PR15222 to ~5x. If 5x is still considered too large, a lower limit can be used as the default. This represents a functionality change, but only for very large inputs (thus, there is no regression test). llvm-svn: 175251
* Revert "Simplify the attributes '<' comparison function."Anna Zaks2013-02-151-13/+15
| | | | | | This reverts commit 82c101153fe7b35bce48781fab038e1b8f31a7bd. llvm-svn: 175250
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-7/+10
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* Simplify the attributes '<' comparison function.Bill Wendling2013-02-151-15/+13
| | | | llvm-svn: 175235
* [mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka2013-02-141-1/+1
| | | | | | | Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. llvm-svn: 175226
* [mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka2013-02-141-86/+83
| | | | | | | defined and used registers. Also add a few helper functions to simplify the code. llvm-svn: 175224
* [mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka2013-02-141-64/+47
| | | | llvm-svn: 175222
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-0/+5
| | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions llvm-svn: 175221
* The operand listing is very much outdated.Eli Bendersky2013-02-141-5/+2
| | | | llvm-svn: 175220
* [mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka2013-02-141-38/+29
| | | | | | | | 1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. llvm-svn: 175219
* BBVectorize: Remove the remaining instances of std::multimapHal Finkel2013-02-141-231/+256
| | | | | | | | | | All instances of std::multimap have now been replaced by DenseMap<K, std::vector<V> >, and this yields a speedup of 5% on the csa.ll test case from PR15222. No functionality change intended. llvm-svn: 175216
* BBVectorize: Don't store candidate pairs in a std::multimapHal Finkel2013-02-141-60/+92
| | | | | | | | | | This is another commit on the road to removing std::multimap from BBVectorize. This gives an ~1% speedup on the csa.ll test case in PR15222. No functionality change intended. llvm-svn: 175215
* Simplify code. Remove "else after return".Jakub Staszak2013-02-141-5/+4
| | | | llvm-svn: 175212
* Update comment.Chad Rosier2013-02-141-1/+2
| | | | llvm-svn: 175209
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
| | | | | | | | This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. llvm-svn: 175205
* s/bool/LLVMBool/Bill Wendling2013-02-141-1/+1
| | | | llvm-svn: 175204
* Add two new functions to the C API:Bill Wendling2013-02-141-0/+23
| | | | | | | | | LLVMCreateMemoryBufferWithMemoryRange - exposes MemoryBuffer::getMemBuffer LLVMCreateMemoryBufferWithMemoryRangeCopy - exposes MemoryBuffer::getMemBufferCopy Patch by Moritz Maxeiner! llvm-svn: 175199
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-145-0/+54
| | | | | | -feature flag, instructions definitions, test cases llvm-svn: 175196
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-145-37/+34
| | | | | | | | | | | | | | | | The important fix is that the constant interpolation value is stored in the parameter slot P0, which is encoded as 2. In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and add a special operand class for the parameter slots for type checking and pretty printing. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175193
* Dont merge consecutive loads/stores into vectors when noimplicitfloat is used.Nadav Rotem2013-02-141-6/+6
| | | | llvm-svn: 175190
* 80-colNadav Rotem2013-02-141-1/+2
| | | | llvm-svn: 175189
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
| | | | | | This patch doesn't introduce any functionality changes. llvm-svn: 175187
* Re-apply r175088 for bug fix 13622: Add paired register support forWeiming Zhao2013-02-142-6/+150
| | | | | | | | inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
| | | | | | | | | It fixes around 100 tfb piglit tests and 16 glean tests. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175183
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
| | | | | | | | This allows MachineInstScheduler to reorder them, and thus make scheduling more efficient. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175182
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
| | | | | | | | | This fixes a couple of regressions on (probably not just) cayman NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175180
* AArch64: switch from neverHasSideEffects to hasSideEffects.Tim Northover2013-02-141-4/+4
| | | | llvm-svn: 175176
* Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola2013-02-141-40/+19
| | | | llvm-svn: 175173
* AArch64: stop claiming that NEON registers are usable for now.Tim Northover2013-02-141-11/+0
| | | | | | | | | | If vector types have legal register classes, then LLVM bypasses LegalizeTypes on them, which causes faults currently since the code to handle them isn't in place. This fixes test failures when AArch64 is the default target. llvm-svn: 175172
* AArch64: add block comments where missingTim Northover2013-02-1419-11/+86
| | | | | | Only comments affected. No code change at all. llvm-svn: 175169
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-141-4/+8
| | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] llvm-svn: 175164
* Workaround an MSan false positive.Evgeniy Stepanov2013-02-141-0/+2
| | | | llvm-svn: 175156
* Add some legality checks for SETCC before introducing it in the DAG combiner ↵Owen Anderson2013-02-141-2/+6
| | | | | | post-operand legalization. llvm-svn: 175149
* Fixed a bug in X86TargetLowering::LowerVectorIntExtend() (assertion failure).Elena Demikhovsky2013-02-141-3/+17
| | | | | | Added a test. llvm-svn: 175144
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
| | | | | | | Fixes assertion failure in newly added lit test. Might just be a bandaid that needs to be revisited. llvm-svn: 175139
* Revert r175120 and r175121. Clang is producing the expected asm names again.Rafael Espindola2013-02-142-1/+7
| | | | llvm-svn: 175133
* RegisterCoalescer::reMaterializeTrivialDef() can constrain the destinationCameron Zwarich2013-02-141-1/+1
| | | | | | register class to match the defining instruction. llvm-svn: 175130
* Teach the DataLayout aware constant folder to be much more aggressive towardsNick Lewycky2013-02-141-8/+30
| | | | | | 'and' instructions. This is a pattern that shows up a lot in ubsan binaries. llvm-svn: 175128
* Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-143-87/+73
| | | | | | | | | up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
* Fix RegisterCoalescer::rematerializeTrivialDef() so that it works on flippedCameron Zwarich2013-02-141-10/+10
| | | | | | | CoalescerPairs. Also, make it take a CoalescerPair directly like other methods of RegisterCoalescer. llvm-svn: 175123
* Fix some issues with rematerialization in RegisterCoalescer when the destinationCameron Zwarich2013-02-141-0/+10
| | | | | | | | | | | | of the copy is a subregister def. The current code assumes that it can do a full def of the destination register, but it is not checking that the def operand is read-undef. It also doesn't clear the subregister index of the destination in the new instruction to reflect the full subregister def. These issues were found running 'make check' with my next commit that enables rematerialization in more cases. llvm-svn: 175122
* Don't assume the mangling of static functions.Rafael Espindola2013-02-141-6/+0
| | | | llvm-svn: 175121
* Don't asume that a static function in an extern "C" block will not be mangled.Rafael Espindola2013-02-141-1/+1
| | | | | | | | | | | | | | Since functions with internal linkage don't have language linkage, it is valid to overload them: extern "C" { static int foo(); static int foo(int); } So we mangle them. llvm-svn: 175120
* temporarily revert the patch due to some conflictsWeiming Zhao2013-02-132-150/+6
| | | | llvm-svn: 175107
* Retain the name of the new internal global that's been shrunk.Bill Wendling2013-02-131-2/+5
| | | | | | | | | It's possible (e.g. after an LTO build) that an internal global may be used for debugging purposes. If that's the case appending a '.b' to it makes it hard to find that variable. Steal the name from the old GV before deleting it so that they can find that variable again. llvm-svn: 175104
* Hexagon: add support for predicate-GPR copies.Anshuman Dasgupta2013-02-131-0/+12
| | | | llvm-svn: 175102
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