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* Do not preset the cc register, the instructions actually use it.Misha Brukman2003-06-051-20/+17
| | | | llvm-svn: 6637
* Minor tuning -- avoid a non-inlinable function call on every operand.Vikram S. Adve2003-06-051-70/+72
| | | | | | Also, reorder a couple of functions for inlining. llvm-svn: 6635
* Fix (bogus) possibly uninitialized warningChris Lattner2003-06-051-1/+1
| | | | llvm-svn: 6634
* Added lazy function resolution to the JIT.Misha Brukman2003-06-052-31/+223
| | | | llvm-svn: 6633
* * The textual output of (non-)predicted FP branches is the same.Misha Brukman2003-06-051-24/+50
| | | | | | | * Stop mapping FBcc instructions to deprecated opcodes, map to FBPcc instead. * Fixed opf in FCMPxy instructions. llvm-svn: 6632
* Fix bug: InstCombine/2003-06-05-BranchInvertInfLoop.llChris Lattner2003-06-051-1/+1
| | | | llvm-svn: 6630
* Implement generation of cmp R, C to not use an extra registerChris Lattner2003-06-052-12/+35
| | | | llvm-svn: 6627
* Special case simple binary operator X op CChris Lattner2003-06-051-27/+55
| | | | | | | | | This avoid generating a register to hold C, which in turn speeds up the register allocator by a lot: ~9% on 164.gzip and ~17% on 256.bzip2. This also speeds up other passes. This also speeds up execution of the program marginally, and makes the asm much easier to read. :) llvm-svn: 6626
* Add instructions for (add|sub|and|or|xor)ri(8|16|32)Chris Lattner2003-06-051-2/+23
| | | | llvm-svn: 6625
* Fix bug: Jello/2003-06-04-bzip2-bug.llChris Lattner2003-06-051-23/+21
| | | | llvm-svn: 6624
* Fixed a bug so initialization code is always inserted in mainAnand Shukla2003-06-052-18/+44
| | | | llvm-svn: 6622
* Use a constant expr GEP instead of an actual instructionChris Lattner2003-06-051-4/+2
| | | | llvm-svn: 6620
* All store instructions really want 'rd' in the first field.Misha Brukman2003-06-051-13/+20
| | | | | | | | Special cases: STFSRx and STXFSRx - they operate on predefined rd=0 or rd=1, and expect %fsr as the parameter in assembly. They are disabled (since not used) until an encoding, both for code generation and output, is chosen. llvm-svn: 6619
* Added missing 'rs1' field to F3_rdrs1imm13, 'rd' to F3_rdrs1rs2.Misha Brukman2003-06-051-3/+2
| | | | llvm-svn: 6618
* lib/CodeGen/Mapping/MappingInfo.cpp:Brian Gaeke2003-06-042-109/+117
| | | | | | | | | | | | | | | | | | | | Update file comment to contain a bunch of the overview mapping-info documentation previously buried within the file. Remove some unnecessary include/using stmts. Rename pass to MappingInfoCollector. Rewrite a lot of it so it doesn't use global instance variables and so it outputs into MappingInfo objects and then dumps those out, instead of going straight to an assembly file. Change name of factory to getMappingInfoCollector. Fold prologue & epilogue writers into MappingInfo methods. lib/Target/Sparc/FInfo.cpp: Correct file comment to reflect above change lib/Target/Sparc/Sparc.cpp: Change name of factory to getMappingInfoCollector. llvm-svn: 6617
* Add file comment. Include <vector> and <string>. Update include guardsBrian Gaeke2003-06-041-5/+32
| | | | | | | to reflect file's current location. Add definition of class MappingInfo. llvm-svn: 6616
* Revert brians patch to get mapping info working againChris Lattner2003-06-041-9/+4
| | | | | | sorry dude llvm-svn: 6615
* Had to comment out a line in outByte() to get it to compile because Out and ↵Tanya Lattner2003-06-041-1/+1
| | | | | | | | tmp were undeclared. I was not sure what Brian wanted, so I will let him fix this. But now it compiles. llvm-svn: 6614
* Make this work with counter > 127Chris Lattner2003-06-041-1/+1
| | | | llvm-svn: 6613
* * Instead of re-inventing the MachineConstantPool emitter that's already givenMisha Brukman2003-06-042-111/+146
| | | | | | | | | | | | | | | | | | | | in Emitter.cpp, just convert the Sparc version of the constant pool into what's already supported and inter-operate. * Implemented a first pass at lazy function resolution in the JITResolver. That required adding a SparcV9CodeEmitter pointer to simplify generating bit-patterns of the instructions. * SparcV9CodeEmitter now creates and destroys static TheJITResolver, which makes sense because the SparcV9CodeEmitter is the only user of TheJITResolver, and lives for the entire duration of the JIT (via PassManager which lives in VM). * Changed all return values in the JITResolver to uint64_t because of the 64-bit Sparc architecture. * Added a new version of getting the value of a GlobalValue in the SparcV9CodeEmitter, which now works for already-generated functions (JITted or library functions). * Removed little-used and unused functions, cleaning up the internal view of the SparcV9CodeEmitter. llvm-svn: 6612
* * Institute a hack for the Sparc call to mmap() to get our generated code to beMisha Brukman2003-06-041-10/+16
| | | | | | | | | | | laid out closer to the VM so that calls to library functions (e.g. puts()) and callback (e.g. JITResolver::CompilationCallback) fit into 30 bits of the call instruction. * Abort if architecture is not yet supported (not X86 or Sparc) because it likely requires a different set of parameters to mmap() . * Stop using hard-coded values for page size; use sysconf(_SC_PAGESIZE) instead. llvm-svn: 6610
* Make writeNumber() void. Get ready to decouple it from .byte directive output.Brian Gaeke2003-06-041-4/+9
| | | | llvm-svn: 6609
* Made changes suggested by ChrisSumant Kowshik2003-06-041-51/+55
| | | | llvm-svn: 6606
* Clean up previous code.Chris Lattner2003-06-041-11/+20
| | | | | | Add new combination to turn seteq X, 0 -> not(cast X to bool) llvm-svn: 6604
* I have finally seen the light. The code to change the opcode must live higher inMisha Brukman2003-06-041-4/+13
| | | | | | | | | | | the loop, and in both cases. In the first case, it is a VReg that is a constant so it may be actually converted to a constant. In the second case, it is already a constant, but then if it doesn't change its type (e.g. to become a register and have the value loaded from memory if it is too large to live in its instruction field), we must change the opcode BEFORE the 'continue', otherwise we miss the opportunity. llvm-svn: 6602
* Added the 4.7 instruction class and all the FMOVcc instructions in them.Misha Brukman2003-06-042-37/+130
| | | | llvm-svn: 6601
* Implement combination of boolean not with branchChris Lattner2003-06-041-0/+14
| | | | llvm-svn: 6599
* Comment out opcodes currently unused in the Sparc backend.Misha Brukman2003-06-041-0/+3
| | | | llvm-svn: 6597
* No really, you _cannot use_ getelementptr on an unsized type: that makesChris Lattner2003-06-041-5/+1
| | | | | | no sense. llvm-svn: 6595
* Added instruction format class 3.15 and floating-point compare instructions.Misha Brukman2003-06-042-11/+22
| | | | llvm-svn: 6594
* Undo one of those last fixes -- it was incorrect.Vikram S. Adve2003-06-041-3/+5
| | | | llvm-svn: 6593
* Sparc's dlsym() requires the special operand RTLD_SELF to find a symbol in theMisha Brukman2003-06-041-0/+4
| | | | | | currently-running process. llvm-svn: 6592
* Avoid generating a getelementptr instruction of a functionChris Lattner2003-06-041-1/+1
| | | | llvm-svn: 6591
* Pass through the emitConstantPool() call to the real emitter.Misha Brukman2003-06-031-0/+4
| | | | llvm-svn: 6590
* Make the write*map methods more self-contained. Document some more.Brian Gaeke2003-06-031-42/+57
| | | | llvm-svn: 6589
* Remove usage of typedefChris Lattner2003-06-031-4/+2
| | | | llvm-svn: 6583
* Add namespace comments for doxygenChris Lattner2003-06-032-5/+6
| | | | llvm-svn: 6581
* I documented this file, in an attempt to understand it, with a view towardBrian Gaeke2003-06-031-56/+73
| | | | | | | | | | | rewriting it. I also vacuumed out all the commented-out code and inaccurate comments, etc. (We need to put the mapping information in a data structure so that we can pass it out to the JIT, instead of automagically converting it to .byte directives.) llvm-svn: 6574
* Use the new -o tablegen optionChris Lattner2003-06-031-4/+1
| | | | llvm-svn: 6572
* Constants are laid out in memory in PC-relative form.Misha Brukman2003-06-031-1/+1
| | | | llvm-svn: 6568
* Added opcode conversion for conditional move of integers.Misha Brukman2003-06-031-0/+50
| | | | llvm-svn: 6567
* * Convert load/store opcodes from register to immediate forms.Misha Brukman2003-06-031-9/+11
| | | | | | * Stop code from wrapping to the next line. llvm-svn: 6566
* Convert load/store opcodes from register to immediate forms, if necessary.Misha Brukman2003-06-031-4/+13
| | | | llvm-svn: 6565
* Store instructions are different from other Format 3.1/3.2 instructions in thatMisha Brukman2003-06-032-7/+43
| | | | | | | they prefer the destination register to be last. Thus, two new classes were made for them that accomodate for having this layout of operands (F3_1rd, F3_2rd). llvm-svn: 6564
* Moved code to modify the opcode from 'reg' to 'imm' form to a more logical ↵Misha Brukman2003-06-031-15/+6
| | | | | | place. llvm-svn: 6563
* * Added section A.34: Move FP register on int reg condition (FMOVr)Misha Brukman2003-06-031-13/+42
| | | | | | | * Labeled sections that are not currently used in the Sparc backend as not requiring completion at this time. llvm-svn: 6562
* * Removed unused classes (rd field is always mentioned last); fixed comments.Misha Brukman2003-06-031-38/+34
| | | | | | | * Added instruction classes which start building from rs1, then rs2, and rd. * Fixed order of operands in classes 4.1 and 4.2; added 4.6 . llvm-svn: 6561
* * Removed unused classes: the rd field is always mentioned as the last reg.Misha Brukman2003-06-031-57/+19
| | | | | | | | | * Added new classes which start building from rs1, adding rs2, and then rd. * Fixed order of operands in classes 3.11, 3.12, 3.16, and 3.17 . * Fixed comments to reflect Real Life (tm). * Removed "don't care" commented out assignments and dead classes (#if 0). llvm-svn: 6560
* The rd field goes after the immediate field in format 2.1 instructions.Misha Brukman2003-06-031-2/+1
| | | | llvm-svn: 6559
* Moved FInfo.cpp to lib/Target/Sparc as it is Sparc-specific.Misha Brukman2003-06-021-73/+0
| | | | llvm-svn: 6554
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