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* Output .eh_frames on COFF too now that the integrated as is used on mingw.Rafael Espindola2013-12-021-0/+1
| | | | llvm-svn: 196104
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-028-14/+23
| | | | llvm-svn: 196102
* XCoreFrameLowering.cpp: Use [in,out] instead of [in] [out]. [-Wdocumentation]NAKAMURA Takumi2013-12-021-2/+2
| | | | llvm-svn: 196094
* XCore target: Make handling of large frames not dependent upon an FP.Robert Lytton2013-12-026-151/+237
| | | | | | | | | | | | eliminateFrameIndex() has been reworked to handle both small & large frames with either a FP or SP. An additional Slot is required for Scavenging spills when not using FP for large frames. Reworked the handling of Register Scavenging. Whether we are using an FP or not, whether it is a large frame or not, and whether we are using a large code model or not are now independent. llvm-svn: 196091
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-026-69/+109
| | | | | | | | | | | | These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
* XCore: Unbreak C++11 build.Benjamin Kramer2013-12-021-3/+3
| | | | llvm-svn: 196089
* XCore target: fix large code model 'select' indirect address handling.Robert Lytton2013-12-021-0/+3
| | | | llvm-svn: 196088
* XCore target: Add large code modelRobert Lytton2013-12-025-28/+175
| | | | | | | | | | | | | | | | When using large code model: Global objects larger than 'CodeModelLargeSize' bytes are placed in sections named with a trailing ".large" The folded global address of such objects are lowered into the const pool. During inspection it was noted that LowerConstantPool() was using a default offset of zero. A fix was made, but due to only offsets of zero being generated, testing only verifies the change is not detrimental. Correct the flags emitted for explicitly specified sections. We assume the size of the object queried by getSectionForConstant() is never greater than CodeModelLargeSize. To handle greater than CodeModelLargeSize, changes to AsmPrinter would be required. llvm-svn: 196087
* XCore target: Fix eliminateFrameIndex() to handle large framesRobert Lytton2013-12-021-7/+18
| | | | | | | | Large frame offsets are loaded from the ConstantPool. Where possible, offsets are encoded using the smaller MKMSK instruction. Large frame offsets can only be used when there is a frame-pointer. llvm-svn: 196085
* XCore target: Enable frames larger than 65535 to be loweredRobert Lytton2013-12-021-138/+177
| | | | llvm-svn: 196084
* [tsan] fix instrumentation of vector vptr updates ↵Kostya Serebryany2013-12-021-4/+7
| | | | | | (https://code.google.com/p/thread-sanitizer/issues/detail?id=43) llvm-svn: 196079
* Remove leftovers from a non-MC asm printer.Rafael Espindola2013-12-022-168/+0
| | | | llvm-svn: 196068
* Remove #if 0 declarations.Rafael Espindola2013-12-021-8/+0
| | | | llvm-svn: 196067
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-0212-86/+8
| | | | llvm-svn: 196065
* Remove dead declarations.Rafael Espindola2013-12-022-8/+0
| | | | llvm-svn: 196063
* Refactor for clarity and efficiency.Rafael Espindola2013-12-021-23/+22
| | | | | | | The PPC GetSymbolFromOperand already prefixed stubs of MO_ExternalSymbol, so this should be a nop. llvm-svn: 196059
* ARM: fix bug in -Oz stack adjustment foldingTim Northover2013-12-014-21/+26
| | | | | | | | | | | Previously, we clobbered callee-saved registers when folding an "add sp, #N" into a "pop {rD, ...}" instruction. This change checks whether a register we're going to add to the "pop" could actually be live outside the function before doing so and should fix the issue. This should fix PR18081. llvm-svn: 196046
* Revamp error checking in the ms inline asm parser.Benjamin Kramer2013-12-011-46/+47
| | | | | | | | | - Actually abort when an error occurred. - Check that the frontend lookup worked when parsing length/size/type operators. Tested by a clang test. PR18096. llvm-svn: 196044
* Use accessor methods instead.Bill Wendling2013-12-011-2/+1
| | | | llvm-svn: 196006
* Use 'unsigned char' to get this past gcc error message:Bill Wendling2013-12-011-3/+4
| | | | | | error: invalid conversion from 'unsigned char' to '{anonymous}::Sequence' llvm-svn: 196004
* Add a scheduling model (with itinerary) for the PPC POWER7Hal Finkel2013-11-304-2/+390
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a scheduling model for the POWER7 (P7) core, and enables the machine-instruction scheduler when targeting the P7. Scheduling for the P7, like earlier ooo PPC cores, requires considering both dispatch group hazards, and functional unit resources and latencies. These are both modeled in a combined itinerary. Dispatch group formation is still handled by the post-RA scheduler (which still needs to be updated for the P7, but nevertheless does a pretty good job). One interesting aspect of this change is that I've also enabled to use of AA duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark results seem to support this decision (see below), and while this is normally useful for in-order cores, and not for ooo cores like the P7, I think that the dispatch slot hazards are enough like in-order resources to make the AA useful. Test suite significant performance differences (where negative is a speedup, and positive is a regression) vs. the current situation: MultiSource/Benchmarks/BitBench/drop3/drop3 with AA: N/A without AA: -28.7614% +/- 19.8356% (significantly against AA) MultiSource/Benchmarks/FreeBench/neural/neural with AA: -17.7406% +/- 11.2712% without AA: N/A (significantly in favor of AA) MultiSource/Benchmarks/SciMark2-C/scimark2 with AA: -11.2079% +/- 1.80543% without AA: -11.3263% +/- 2.79651% MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt with AA: -41.8649% +/- 17.0053% without AA: -34.5256% +/- 23.7072% MultiSource/Benchmarks/mafft/pairlocalalign with AA: 25.3016% +/- 17.8614% without AA: 38.6629% +/- 14.9391% (significantly in favor of AA) MultiSource/Benchmarks/sim/sim with AA: N/A without AA: 13.4844% +/- 7.18195% (significantly in favor of AA) SingleSource/Benchmarks/BenchmarkGame/Large/fasta with AA: 15.0664% +/- 6.70216% without AA: 12.7747% +/- 8.43043% SingleSource/Benchmarks/BenchmarkGame/puzzle with AA: 82.2713% +/- 26.3567% without AA: 75.7525% +/- 41.1842% SingleSource/Benchmarks/Misc/flops-2 with AA: -37.1621% +/- 20.7964% without AA: -35.2342% +/- 20.2999% (significantly in favor of AA) These are 99.5% confidence intervals from 5 runs per configuration. Regarding the choice to turn on AA during CodeGen, of these results, four seem significantly in favor of using AA, and one seems significantly against. I'm not making this decision based on these numbers alone, but these results seem consistent with results I have from other tests, and so I think that, on balance, using AA is a win. llvm-svn: 195981
* Split some PPC itinerary classesHal Finkel2013-11-3011-31/+154
| | | | | | | | | | | | | In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-301-1/+3
| | | | llvm-svn: 195975
* [mips][msa] MSA loads and stores have a 10-bit offset. Account for this when ↵Daniel Sanders2013-11-301-5/+47
| | | | | | | | | lowering FrameIndex. This prevents the compiler from emitting invalid ld.[bhwd]'s and st.[bhwd]'s when the stack frame is between 512 and 32,768 bytes in size. llvm-svn: 195973
* [mips][msa] A small refactor to reduce patch noise in my next commitDaniel Sanders2013-11-301-15/+17
| | | | | | No functional change. An if-statement has been split into two nested if-statements. llvm-svn: 195972
* Reverse the order of eviction checks for possible compile time savings. No ↵Andrew Trick2013-11-291-3/+3
| | | | | | functionality. llvm-svn: 195969
* Part 1 of 3 patches that completes very long conditional branchesReed Kotler2013-11-292-16/+44
| | | | | | | | | | | | in constant islands for Mips16. We introdcuce JalB16 as a synomnym for Jal16. It makes it easier to read and is also necessary because Jal16 is a call instruction but JalB16 is being used as a branch. Various parts of LLVM will not work properly even in this late stage of the backend if we use what was declared as a call instruction to function as a branch. For one, basic block labels may not get emitted in some situations. llvm-svn: 195968
* Revert revision 195965.Zoran Jovanovic2013-11-291-3/+1
| | | | llvm-svn: 195967
* Fixed issue with microMIPS long branch.Zoran Jovanovic2013-11-291-1/+3
| | | | llvm-svn: 195965
* Adjust PPC A2 input operand latenciesHal Finkel2013-11-291-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the PPC A2, instructions are only issued after their input operands are ready. Model this by specifying that input operands are read at dispatch (0 cycles after issue). This changes all input operand latencies from 1 to 0. Significant test-suite performance changes (these are 99.5% confidence intervals on 6 runs for both before and after): speedups: MultiSource/Benchmarks/sim/sim -1.21915% +/- 0.175063% MultiSource/Benchmarks/TSVC/LinearDependence-flt/LinearDependence-flt -1.23946% +/- 1.05133% SingleSource/Benchmarks/Misc/flops-2 -1.24237% +/- 0.681362% MultiSource/Applications/JM/lencod/lencod -1.33992% +/- 0.757498% MultiSource/Benchmarks/TSVC/InductionVariable-flt/InductionVariable-flt -1.51802% +/- 1.21468% MultiSource/Benchmarks/TSVC/GlobalDataFlow-flt/GlobalDataFlow-flt -2.18818% +/- 1.28605% MultiSource/Benchmarks/TSVC/Packing-flt/Packing-flt -2.21977% +/- 1.19499% SingleSource/Benchmarks/BenchmarkGame/spectral-norm -2.29822% +/- 0.671871% MultiSource/Benchmarks/TSVC/Packing-dbl/Packing-dbl -2.40975% +/- 0.355931% SingleSource/Benchmarks/Misc/fp-convert -2.41899% +/- 1.04751% MultiSource/Benchmarks/TSVC/Searching-dbl/Searching-dbl -2.50349% +/- 0.126765% SingleSource/Benchmarks/Misc/flops-3 -3.00214% +/- 0.700795% MultiSource/Benchmarks/TSVC/LoopRestructuring-flt/LoopRestructuring-flt -3.56995% +/- 3.2929% MultiSource/Applications/sgefa/sgefa -4.24908% +/- 2.00413% MultiSource/Benchmarks/ASC_Sequoia/IRSmk/IRSmk -18.1294% +/- 3.96489% regressions: MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl 1.03249% +/- 0.178547% MultiSource/Applications/hexxagon/hexxagon 1.16597% +/- 0.285235% MultiSource/Benchmarks/TSVC/IndirectAddressing-flt/IndirectAddressing-flt 1.39576% +/- 1.07855% SingleSource/Benchmarks/Misc-C++/stepanov_v1p2 1.71539% +/- 0.173182% MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1 1.90013% +/- 0.866472% MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl 2.39854% +/- 1.05914% MultiSource/Benchmarks/TSVC/ControlFlow-dbl/ControlFlow-dbl 2.4402% +/- 0.817904% MultiSource/Benchmarks/TSVC/LoopRestructuring-dbl/LoopRestructuring-dbl 5.87997% +/- 3.3172% MultiSource/Benchmarks/Trimaran/netbench-crc/netbench-crc 9.02643% +/- 5.79591% MultiSource/Benchmarks/VersaBench/bmm/bmm 10.3517% +/- 1.227% Obviously, there are data points on both sides of this; but I think, overall, this supports making the change. llvm-svn: 195951
* Teach LocalStackSlotAllocation that stackmaps/patchpoints don't have rangeLang Hames2013-11-291-3/+5
| | | | | | constraints on their frame offsets. llvm-svn: 195950
* Create a PPC440 SchedMachineModelHal Finkel2013-11-292-6/+20
| | | | | | | Some of the older PPC processor definitions don't have associated SchedMachineModels; correct this for the PPC440. llvm-svn: 195949
* Fixup PPC440 load/store operand latenciesHal Finkel2013-11-291-19/+19
| | | | | | | | The operand latencies for loads and stores in the PPC440 itinerary were wrong (the store operands are all inputs, and the "with update" (pre-increment) instructions need a latency for the additional output). llvm-svn: 195948
* Adjust PPC440 operand latenciesHal Finkel2013-11-291-54/+54
| | | | | | | | | | | | The operand latencies for the PPC440 should be specified relative to dispatch, not relative to the initial fetch-and-decode stages. Because most instructions (ignoring bypass) wait in dispatch until their operands are ready, this is modeled as reading input operands "at dispatch" (0 cycles after issue), and so every input and output operand has 4 cycles subtracted from it. This could alter scheduling slightly, but I don't expect a large effect. llvm-svn: 195947
* Don't model the fetch and decode units for the PPC440Hal Finkel2013-11-291-180/+61
| | | | | | | | | | Modeling the fetch and decode units in the PPC440 itinerary does not add anything to the hazard detection capability (and so modeling them just wastes compile time). No functionality change intended. llvm-svn: 195946
* Remove unused variable from r195944.Lang Hames2013-11-291-1/+0
| | | | llvm-svn: 195945
* Refactor a lot of patchpoint/stackmap related code to simplify and make itLang Hames2013-11-299-232/+211
| | | | | | | | | | | | | | | | | | | | | | target independent. Most of the x86 specific stackmap/patchpoint handling was necessitated by the use of the native address-mode format for frame index operands. PEI has now been modified to treat stackmap/patchpoint similarly to DEBUG_INFO, allowing us to use a simple, platform independent register/offset pair for frame indexes on stackmap/patchpoints. Notes: - Folding is now platform independent and automatically supported. - Emiting patchpoints with direct memory references now just involves calling the TargetLoweringBase::emitPatchPoint utility method from the target's XXXTargetLowering::EmitInstrWithCustomInserter method. (See X86TargetLowering for an example). - No more ugly platform-specific operand parsers. This patch shouldn't change the generated output for X86. llvm-svn: 195944
* AArch64: The pattern match should check the range of the immediate value.Hao Liu2013-11-291-113/+123
| | | | | | | Or we can generate some illegal instructions. E.g. shrn2 v0.4s, v1.2d, #35. The legal range should be in [1, 16]. llvm-svn: 195941
* Add missing pattern for supporting intrinsic function vbsl_f64 withJiangning Liu2013-11-291-0/+3
| | | | | | argument double floating point. llvm-svn: 195938
* [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction.Kevin Qin2013-11-292-35/+73
| | | | llvm-svn: 195936
* Rein in overzealous InstCombine of fptrunc(OP(fpextend, fpextend)).Stephen Canon2013-11-281-26/+82
| | | | llvm-svn: 195934
* Refactor to remove a bit of duplication. No functionality change.Rafael Espindola2013-11-281-24/+24
| | | | llvm-svn: 195933
* Silence sign-compare warning and reduce nesting.Benjamin Kramer2013-11-281-7/+7
| | | | | | No functionality change. llvm-svn: 195932
* Remove an always true parameter.Rafael Espindola2013-11-281-6/+2
| | | | llvm-svn: 195931
* [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.NAKAMURA Takumi2013-11-2811-22/+0
| | | | | | | | | | I think, in principle, intrinsics_gen may be added explicitly. That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen. Almost all source files depend on both CommonTaleGen and intrinsics_gen. Explicit add_dependencies() have been pruned under lib/Target. llvm-svn: 195929
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-2861-109/+11
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* The global prefix is always one char. Don't use a string for it.Rafael Espindola2013-11-285-13/+8
| | | | llvm-svn: 195926
* [CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi2013-11-2816-35/+0
| | | | | | I forgot to commit them. They were staging in my local repo. llvm-svn: 195924
* [mips] Revert test commit r195922.Daniel Sanders2013-11-281-1/+0
| | | | llvm-svn: 195923
* [mips] A test commit to test my Herald and Audit workflowDaniel Sanders2013-11-281-0/+1
| | | | | | Will be reverted in the next commit llvm-svn: 195922
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