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* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-1217-69/+665
| | | | | | | | | | | | | | | | getArithmeticInstrCost(), getShuffleCost(), getCastInstrCost(), getCmpSelInstrCost(), getVectorInstrCost(), getMemoryOpCost(), getInterleavedMemoryOpCost() implemented. Interleaved access vectorization enabled. BasicTTIImpl::getCastInstrCost() improved to check for legal extending loads, in which case the cost of the z/sext instruction becomes 0. Review: Ulrich Weigand, Renato Golin. https://reviews.llvm.org/D29631 llvm-svn: 300052
* [DWARF] Fix compiler warnings in DWARFContext.cpp, NFCiKrasimir Georgiev2017-04-121-2/+1
| | | | llvm-svn: 300051
* [AMDGPU] SDWA: make pass globalSam Kolton2017-04-121-183/+175
| | | | | | | | | | | | Summary: Remove checks for basic blocks. Reviewers: vpykhtin, rampitec, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D31935 llvm-svn: 300040
* [DWARF] - Refactoring of DWARFContextInMemory implementation.George Rimar2017-04-121-64/+71
| | | | | | | | | | | | | | This change is basically relative to D31136, where I initially wanted to implement some relocations handling optimization which shows it can give significant boost. Though even without any caching algorithm looks code can have some cleanup at first. Refactoring separates out code for taking symbol address, used in relocations computation. Differential revision: https://reviews.llvm.org/D31747 llvm-svn: 300039
* [LoadCombine] Avoid analysing dead basic blocksBjorn Pettersson2017-04-121-1/+12
| | | | | | | | | | | | | | | | | | | | | Summary: Dead basic blocks may be forming a loop, for which SSA form is fulfilled, but with a circular def-use chain. LoadCombine could enter an infinite loop when analysing such dead code. This patch solves the problem by simply avoiding to analyse all basic blocks that aren't forward reachable, from function entry, in LoadCombine. Fixes https://bugs.llvm.org/show_bug.cgi?id=27065 Reviewers: mehdi_amini, chandlerc, grosser, Bigcheese, davide Reviewed By: davide Subscribers: dberlin, zzheng, bjope, grandinj, Ka-Ka, materi, jholewinski, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D31032 llvm-svn: 300034
* [IR] Redesign the case iterator in SwitchInst to actually be an iteratorChandler Carruth2017-04-1223-114/+101
| | | | | | | | | | | | | | | | and to expose a handle to represent the actual case rather than having the iterator return a reference to itself. All of this allows the iterator to be used with common STL facilities, standard algorithms, etc. Doing this exposed some missing facilities in the iterator facade that I've fixed and required some work to the actual iterator to fully support the necessary API. Differential Revision: https://reviews.llvm.org/D31548 llvm-svn: 300032
* [InstCombine][IR] Add a commutable BinOp matcher. Use it to reduce some ↵Craig Topper2017-04-121-2/+1
| | | | | | code. NFC llvm-svn: 300030
* [BPI] Refactor post domination calculation and simple fix for ColdCallSerguei Katkov2017-04-121-46/+73
| | | | | | | | | | | | | | | | | | | | Collection of PostDominatedByUnreachable and PostDominatedByColdCall have been split out of heuristics itself. Update of the data happens now for each basic block (before update for PostDominatedByColdCall might be skipped if unreachable or matadata heuristic handled this basic block). This separation allows re-ordering of heuristics without loosing the post-domination information. Reviewers: sanjoy, junbuml, vsk, chandlerc, reames Reviewed By: chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31701 llvm-svn: 300029
* [INC] Test commit. NFC.Serguei Katkov2017-04-121-1/+1
| | | | | | Just an update of comment. llvm-svn: 300026
* [AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing.Kannan Narayanan2017-04-125-1/+1881
| | | | | | Based on comments in https://reviews.llvm.org/D31161. llvm-svn: 300023
* CodeGen: BlockPlacement: Clear ComputedEdges between functions.Kyle Butt2017-04-121-2/+5
| | | | | | | | Not clearing was causing non-deterministic compiles for large files. Addresses for MachineBasicBlocks would end up colliding and we would lay out a block that we assumed had been pre-computed when it had not been. llvm-svn: 300022
* ThinLTOBitcodeWriter: keep comdats together, rename if leader is renamedBob Haarman2017-04-121-6/+33
| | | | | | | | | | | | | | | | | | | Summary: COFF requires that every comdat contain a symbol with the same name as the comdat. ThinLTOBitcodeWriter renames symbols, which may cause this requirement to be violated. This change avoids such violations by renaming comdats if their leaders are renamed. It also keeps comdats together when splitting modules. Reviewers: pcc, mehdi_amini, tejohnson Reviewed By: pcc Subscribers: rnk, Prazek, llvm-commits Differential Revision: https://reviews.llvm.org/D31963 llvm-svn: 300019
* Revert "[WebAssembly] Update use of Attributes after r299875"Derek Schuff2017-04-121-14/+17
| | | | | | | | This reverts commit 2a0eb61dcccb15058d5b2a572bb3da0cf47fd550, r300015 I raced with rnk on the commit. llvm-svn: 300016
* [WebAssembly] Update use of Attributes after r299875Derek Schuff2017-04-121-17/+14
| | | | | | This fixes the failing WebAssemblyLowerEmscriptenEHSjLj tests llvm-svn: 300015
* [IR] Add AttributeSet to hide AttributeSetNode* again, NFCReid Kleckner2017-04-1211-182/+268
| | | | | | | | | | | | | | | | | Summary: For now, it just wraps AttributeSetNode*. Eventually, it will hold AvailableAttrs as an inline bitset, and adding and removing enum attributes will be super cheap. This sinks AttributeSetNode back down to lib/IR/AttributeImpl.h. Reviewers: pete, chandlerc Subscribers: llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D31940 llvm-svn: 300014
* Remove xgene1 from host detectionYi Kong2017-04-111-11/+1
| | | | | | | | | This is not a supported mcpu tuning option. We should treat it as "generic" variant. Also, add record for cortex-a35. llvm-svn: 300003
* AMDGPU: Insert wait at start of callee functionsMatt Arsenault2017-04-111-0/+14
| | | | llvm-svn: 300000
* AMDGPU: Refactor SIMachineFunctionInfo slightlyMatt Arsenault2017-04-113-16/+38
| | | | | | Prepare for handling non-entry functions. llvm-svn: 299999
* AMDGPU: Refactor argument loweringMatt Arsenault2017-04-1110-276/+375
| | | | | | | Split into smaller functions and prepare for handling non-entry functions. llvm-svn: 299998
* AMDGPU: Fix folding reg_sequence into copy to phys regMatt Arsenault2017-04-111-0/+4
| | | | | | | This was producing an illegal reg_sequence defining a physical register with virtual register inputs. llvm-svn: 299997
* AMDGPU: Prune unecessary includeMatt Arsenault2017-04-111-2/+0
| | | | llvm-svn: 299996
* [asan] Give global metadata private linkage.Evgeniy Stepanov2017-04-111-5/+6
| | | | | | | Internal linkage preserves names like "__asan_global_foo" which may account to 2% of unstripped binary size. llvm-svn: 299995
* [AArch64] Fix scheduling info for INS(vector, general) instruction.Balaram Makam2017-04-112-1/+6
| | | | llvm-svn: 299994
* InstSimplify: A shuffle of a splat is always the splat itselfZvi Rackover2017-04-111-4/+16
| | | | | | | | | | | | | | | | Summary: Fold: shuffle (splat-shuffle), undef, M --> splat-shuffle Reviewers: spatel, RKSimon, craig.topper Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31527 llvm-svn: 299990
* [x86] Relax the check in areLoadsFromSameBasePtrEaswaran Raman2017-04-111-19/+16
| | | | | | | | | Check if the scale operand is identical (doesn't have to be 1) and do not check the chaain operand. Differential revision: https://reviews.llvm.org/D31833 llvm-svn: 299986
* [LV] Avoid vectorizing first order recurrence when phi uses are outside loopAnna Thomas2017-04-112-5/+20
| | | | | | | | | | | | | | | | | | In the vectorization of first order recurrence, we vectorize such that the last element in the vector will be the one extracted to pass into the scalar remainder loop. However, this is not true when there is a phi (other than the primary induction variable) is used outside the loop. In such a case, we need the value from the second last iteration (i.e. the phi value), not the last iteration (which would be the phi update). I've added a test case for this. Also see PR32396. A follow up patch would generate the correct code gen for such cases, and turn this vectorization on. Differential Revision: https://reviews.llvm.org/D31910 Reviewers: mssimpso llvm-svn: 299985
* MemorySSA: Move to Analysis, from Transforms/Utils. It's used asDaniel Berlin2017-04-1110-13/+13
| | | | | | | | Analysis, it has Analysis passes, and once NewGVN is made an Analysis, this removes the cross dependency from Analysis to Transform/Utils. NFC. llvm-svn: 299980
* MIR: Allow parsing of empty machine functionsJustin Bogner2017-04-112-5/+4
| | | | | | | | | | | | If you run llc -stop-after=codegenprepare and feed the resulting MIR to llc -start-after=codegenprepare, you'll have an empty machine function since we haven't run any isel yet. Of course, this only works if the MIRParser believes you that this is okay. This is essentially a revert of r241862 with a fix for the problem it was papering over. llvm-svn: 299975
* [AArch64] Simplify MacroFusionEvandro Menezes2017-04-111-79/+89
| | | | | | | | | | | | This patch assumes that the dependents to be scanned for the ExitSU are its predecessors; otherwise, the successors of the instr are scanned. Furthermore, sometimes the ExitSU was being fused twice, since it may be fused once when scanning the successors from the beginning of the BB and then again when scanning the predecessors of ExitSU. Thus, when scanning the successors of an instr, skip the ExitSU. llvm-svn: 299974
* [X86] Create the correct ADC/SBB SDNode when lowering add.Davide Italiano2017-04-111-2/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D31911 llvm-svn: 299973
* [AddDiscriminators] Assign discriminators to MemIntrinsic calls.Andrea Di Biagio2017-04-111-1/+15
| | | | | | | | | | | | | | | | | | | | | | | Before this patch, pass AddDiscriminators always avoided to assign discriminators to intrinsic calls. This was done mainly for two reasons: 1) We wanted to minimize the number of based discriminators used. 2) We wanted to avoid non-deterministic discriminator assignment for different debug levels. Unfortunately, that approach was problematic for MemIntrinsic calls. MemIntrinsic calls can be split by SROA into loads and stores, and each new load/store instruction would obtain the debug location from the original intrinsic call. If we don't assign a discriminator to MemIntrinsic calls, then we cannot correctly set the discriminator for the newly created loads and stores. This may have a negative impact on the basic block weight computation performed by the SampleLoader. This patch fixes the issue by letting MemIntrinsic calls have a discriminator. Differential Revision: https://reviews.llvm.org/D31900 llvm-svn: 299972
* Fix spelling compliment->complement. Mostly refering to 2s complement. NFCCraig Topper2017-04-114-6/+6
| | | | llvm-svn: 299970
* [libFuzzer] fix type in signal name.Vitaly Buka2017-04-111-1/+1
| | | | | | | | Fixes PR32576. Patch by Jakub Zawadzki. llvm-svn: 299968
* [InstCombine] Use ConstantExpr::getBinOpIdentity to implement getIdentityValue.Craig Topper2017-04-111-7/+2
| | | | | | This removes a TODO in getIdentityValue and may allow some transforms to occur earlier. But I was unable to find any transforms we didn't already handle. llvm-svn: 299966
* [AMDGPU] Add A5 to data layout for amdgiz environmentYaxun Liu2017-04-111-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D31589 llvm-svn: 299964
* [PDB] Emit index/offset pairs for TPI and IPI streamsReid Kleckner2017-04-112-21/+51
| | | | | | | | | | | | | | | | | | | Summary: This lets PDB readers lookup type record data by type index in O(log n) time. It also enables makes `cvdump -t` work on PDBs produced by LLD. cvdump will not dump a PDB that doesn't have an index-to-offset table. The table is sorted by type index, and has an entry every 8KB. Looking up a type record by index is a binary search of this table, followed by a scan of at most 8KB. Reviewers: ruiu, zturner, inglorion Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31636 llvm-svn: 299958
* revert r299851 - [InstCombine] fix matching of or-of-icmps constants (PR32524)Sanjay Patel2017-04-111-16/+12
| | | | | | This is a candidate culprit for multiple bot fails, so reverting pending investigation. llvm-svn: 299955
* Module::getOrInsertFunction is using C-style vararg instead of variadic ↵Serge Guelton2017-04-1122-177/+145
| | | | | | | | | | | templates. From a user prospective, it forces the use of an annoying nullptr to mark the end of the vararg, and there's not type checking on the arguments. The variadic template is an obvious solution to both issues. Differential Revision: https://reviews.llvm.org/D31070 llvm-svn: 299949
* Remove unused functions. Remove static qualifier from functions in header ↵Vassil Vassilev2017-04-115-55/+0
| | | | | | files. NFC. llvm-svn: 299947
* [AVR] Migrate to new MCAsmBackend applyFixupJonathan Roelofs2017-04-112-2/+2
| | | | | | | | https://reviews.llvm.org/D31875 Patch by Leslie Zhai! llvm-svn: 299946
* [ARM] Refactor Thumb2 sat instructionsSam Parker2017-04-111-48/+30
| | | | | | | | | Refactor the USAT, SSAT, USAT16 and SSAT16 instruction descriptions for Thumb2. Differential Revision: https://reviews.llvm.org/D31933 llvm-svn: 299945
* [GVNHoist] Re-enable GVNHoist by defaultGeoff Berry2017-04-111-3/+3
| | | | | | Turn GVNHoist back on by default now that PR32153 has been fixed. llvm-svn: 299944
* [SDAG] Factor CandidateMatch check into lambda. NFC.Nirav Dave2017-04-111-28/+29
| | | | llvm-svn: 299939
* [SDAG] Factor ChainMerge into helper function NFCI.Nirav Dave2017-04-111-20/+27
| | | | llvm-svn: 299938
* [SDAG] Reorder expensive StoreMerge Check after cheaper one. NFCNirav Dave2017-04-111-8/+9
| | | | llvm-svn: 299937
* [StripDeadDebug/DIFinder] Track inlined SPsKeno Fischer2017-04-112-5/+14
| | | | | | | | | | | | | | | | | | | | Summary: In rL299692 I improved strip-dead-debug-info's ability to drop CUs that are not referenced from the current module. However, in doing so I neglected to realize that some SPs could be referenced entirely from inlined functions. It appears I was not the only one to make this mistake, because DebugInfoFinder, doesn't find those SPs either. Fix this in DebugInfoFinder and then use that to make sure not to drop those CUs in strip-dead-debug-info. Reviewers: aprantl Reviewed By: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31904 llvm-svn: 299936
* Add MachineRegionInfoPassID to Passes.h.Jan Sjodin2017-04-111-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D31899 llvm-svn: 299932
* GlobalISel: Allow legalizing G_FADD to a libcallDiana Picus2017-04-112-0/+7
| | | | | | | | | Use the same handling in the generic legalizer code as for the other libcalls (G_FREM, G_FPOW). Enable it on ARM for float and double so we can test it. llvm-svn: 299931
* [GlobalISel] LegalizerInfo: Enable legalization of non-power-of-2 typesVolkan Keles2017-04-111-6/+9
| | | | | | | | | | | | | | Summary: Legalize only if the type is marked as Legal or Custom. If not, return Unsupported as LegalizerHelper is not able to handle non-power-of-2 types right now. Reviewers: qcolombet, aditya_nandakumar, dsanders, t.p.northover, kristof.beyls, javed.absar, ab Reviewed By: kristof.beyls, ab Subscribers: dberris, rovka, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D31711 llvm-svn: 299929
* Revert "Turn some C-style vararg into variadic templates"Diana Picus2017-04-1122-117/+160
| | | | | | | This reverts commit r299925 because it broke the buildbots. See e.g. http://lab.llvm.org:8011/builders/clang-cmake-armv7-a15/builds/6008 llvm-svn: 299928
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