summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Thumb2 ADR assembly parsing w/o the .w suffix.Jim Grosbach2011-12-151-0/+4
| | | | llvm-svn: 146710
* Make sure we correctly note the existence of an i8 immediate for vblendvps ↵Eli Friedman2011-12-152-3/+3
| | | | | | and friends, so we compute fixups correctly. PR11586. llvm-svn: 146709
* Move parts of lib/Target that use CodeGen into lib/CodeGen.Nick Lewycky2011-12-156-33/+34
| | | | llvm-svn: 146702
* Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a ↵Eli Friedman2011-12-151-1/+1
| | | | | | value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) llvm-svn: 146700
* ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.Jim Grosbach2011-12-151-0/+32
| | | | llvm-svn: 146699
* [asan] add the name of the module to the description of a global variable. ↵Kostya Serebryany2011-12-151-1/+5
| | | | | | This improves the readability of global-buffer-overflow reports. llvm-svn: 146698
* Add MCTargetDesc library to Hexagon targetTony Linthicum2011-12-1515-30/+186
| | | | llvm-svn: 146692
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-153-30/+23
| | | | llvm-svn: 146691
* Enable proper constant island alignment by default.Jakob Stoklund Olesen2011-12-151-1/+1
| | | | | | | The code size increase is tiny (< 0.05%) because so little code uses 16-byte constant pool entries. llvm-svn: 146690
* Add missing zmovl AVX patterns which were causing crashes.Chad Rosier2011-12-151-0/+6
| | | | | | Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! llvm-svn: 146689
* [asan] fix a bug (issue 19) where dlclose and the following mmap caused a ↵Kostya Serebryany2011-12-152-5/+32
| | | | | | false positive. compiler part. llvm-svn: 146688
* Silence warning.Jim Grosbach2011-12-151-1/+1
| | | | llvm-svn: 146686
* ARM NEON two-register double spaced register list parsing support.Jim Grosbach2011-12-151-14/+49
| | | | llvm-svn: 146685
* Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.Chad Rosier2011-12-151-2/+4
| | | | | | Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>! llvm-svn: 146684
* Fix VSELECT operand order. Was previously backwards, causing bogus vector ↵Lang Hames2011-12-151-3/+3
| | | | | | shift results - <rdar://problem/10559581>. llvm-svn: 146671
* Update DebugLoc while merging nodes at -O0.Devang Patel2011-12-152-6/+21
| | | | | | Patch by Kyriakos Georgiou! llvm-svn: 146670
* Virtual table holder field is either metadata or null. Devang Patel2011-12-151-1/+1
| | | | llvm-svn: 146665
* Ensure that the nop that should follow a bl call in PPC64 ELF actually doesHal Finkel2011-12-152-0/+14
| | | | llvm-svn: 146664
* Pass optLevel to XCoreDAGToDAGISel.Richard Osborne2011-12-153-6/+8
| | | | | | Patch by Kyriakos Georgiou. llvm-svn: 146656
* Make constant folding for GEPs a bit more aggressive.Eli Friedman2011-12-151-1/+1
| | | | llvm-svn: 146639
* Don't try to form FGETSIGN after legalization; it is possible in some cases, ↵Eli Friedman2011-12-151-1/+2
| | | | | | but the existing code can't do it correctly. PR11570. llvm-svn: 146630
* Use SmallVector/assign(), rather than std::vector/push_back().Chad Rosier2011-12-151-10/+6
| | | | llvm-svn: 146627
* Add support for lowering fneg when AVX is enabled.Chad Rosier2011-12-151-11/+11
| | | | | | rdar://10566486 llvm-svn: 146625
* Added InstCombine for "select cond, ~cond, x" type patternsPete Cooper2011-12-151-0/+7
| | | | | | These can be reduced to "~cond & x" or "~cond | x" llvm-svn: 146624
* Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. ↵Owen Anderson2011-12-151-0/+22
| | | | | | These are already marked as illegal by default. llvm-svn: 146623
* Make loop preheader insertion in LoopSimplify handle the case where the loop ↵Eli Friedman2011-12-151-16/+34
| | | | | | header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575. llvm-svn: 146621
* Re-re-enable compact unwind after fixing a failure in ↵Bill Wendling2011-12-151-2/+1
| | | | | | SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order. llvm-svn: 146617
* Another improvement to the implementation of .incbin directive by avoiding aKevin Enderby2011-12-151-5/+2
| | | | | | buffer copy. Suggestion by Chris Lattner! llvm-svn: 146614
* The saved registers weren't being processed in the correct order. This lead toBill Wendling2011-12-141-11/+14
| | | | | | | | the compact unwind claiming that one register was saved before another, which isn't all that great in general. Process them in the natural order. Reverse the list only when necessary for the algorithm. llvm-svn: 146612
* Move Instruction::isSafeToSpeculativelyExecute out of VMCore andDan Gohman2011-12-148-63/+76
| | | | | | | | | into Analysis as a standalone function, since there's no need for it to be in VMCore. Also, update it to use isKnownNonZero and other goodies available in Analysis, making it more precise, enabling more aggressive optimization. llvm-svn: 146610
* Consider CPE alignment in CreateNewWater().Jakob Stoklund Olesen2011-12-141-104/+117
| | | | | | | | | | | An aligned constant pool entry may require extra alignment padding where the new water is created. Take that into account when computing offset. Also consider the alignment of other constant pool entries when splitting a basic block. Alignment padding may make it necessary to move the split point higher. llvm-svn: 146609
* ARM NEON better assembly operand range checking for lane indices of VLD/VST.Jim Grosbach2011-12-142-33/+93
| | | | llvm-svn: 146608
* ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.Jim Grosbach2011-12-142-196/+420
| | | | llvm-svn: 146605
* Do not sink instruction, if it is not profitable.Devang Patel2011-12-141-13/+76
| | | | | | | | On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator. Radar 10266272. llvm-svn: 146604
* Reapply r146481 with a fix to create the Builder value in the correct place andBill Wendling2011-12-141-6/+35
| | | | | | | with the correct iterator. <rdar://problem/10530851> llvm-svn: 146600
* Improve the implementation of .incbin directive by replacing a loop by usingKevin Enderby2011-12-141-4/+4
| | | | | | getStreamer().EmitBytes. Suggestion by Benjamin Kramer! llvm-svn: 146599
* LSR: Fold redundant bitcasts on-the-fly.Andrew Trick2011-12-141-3/+8
| | | | llvm-svn: 146597
* ARM NEON fix alignment encoding for VST2 w/ writeback.Jim Grosbach2011-12-141-4/+4
| | | | | | Add tests for w/ writeback instruction parsing and encoding. llvm-svn: 146594
* Add the .incbin directive which takes the binary data from a file and emitsKevin Enderby2011-12-141-0/+49
| | | | | | it to the streamer. rdar://10383898 llvm-svn: 146592
* Nuke old code. Missed in last commit.Jim Grosbach2011-12-141-14/+0
| | | | llvm-svn: 146590
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-144-54/+130
| | | | | | | In addition to improving the representation, this adds support for assembly parsing of these instructions. llvm-svn: 146588
* ARM NEON improve factoring a bit. No functional change.Jim Grosbach2011-12-141-18/+12
| | | | llvm-svn: 146585
* Model ARM predicated write as read-mod-write. e.g.Evan Cheng2011-12-143-16/+47
| | | | | | | | | | | r0 = mov #0 r0 = moveq #1 Then the second instruction has an implicit data dependency on the first instruction. Sadly I have yet to come up with a small test case that demonstrate the post-ra scheduler taking advantage of this. llvm-svn: 146583
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-145-76/+52
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* Fix for bug #11429: Wrong behaviour for switches. Small improvement for code ↵Stepan Dyatkovskiy2011-12-141-11/+82
| | | | | | size heuristics. llvm-svn: 146578
* It turns out that clang does use pointer-to-function types toDan Gohman2011-12-141-2/+6
| | | | | | point to ARC-managed pointers sometimes. This fixes rdar://10551239. llvm-svn: 146577
* Fix speling and 80-col.Jakob Stoklund Olesen2011-12-141-4/+3
| | | | llvm-svn: 146575
* Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct objectAkira Hatanaka2011-12-144-6/+32
| | | | | | | emission is not supported yet, but a patch that adds the support should follow soon. llvm-svn: 146572
* Fix copy/pasto that skipped the 'modify' step.Jim Grosbach2011-12-141-4/+4
| | | | llvm-svn: 146571
* ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach2011-12-142-0/+4
| | | | llvm-svn: 146570
OpenPOWER on IntegriCloud