summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Check length of string before we walk off the end of it.Reid Spencer2007-04-161-3/+3
| | | | | | Thanks, Chris. llvm-svn: 36155
* Update module pass manager to support module passes that requireDevang Patel2007-04-161-11/+44
| | | | | | function passes. llvm-svn: 36154
* Give each pass manager chance to manage lower level analysis pass, which isDevang Patel2007-04-161-20/+60
| | | | | | pass required by one of pass managed by the manager. llvm-svn: 36153
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-1631-348/+358
| | | | | | target for tabs checking. llvm-svn: 36146
* Regenerate.Reid Spencer2007-04-162-17/+19
| | | | llvm-svn: 36144
* Use a more optimal way to get the name of a function. Thanks, Chris.Reid Spencer2007-04-161-1/+2
| | | | llvm-svn: 36143
* Don't return 0 if the len == 5, let the assert handle that case.Reid Spencer2007-04-161-1/+1
| | | | | | Thanks, Chris. llvm-svn: 36139
* For PR1336:Reid Spencer2007-04-161-1/+1
| | | | | | | Subtarget option names must be given in lower case in order to be recognized. Fixes test/CodeGen/Alpha/ctlz.ll llvm-svn: 36125
* Fix test/CodeGen/Generic/vector-constantexpr.llReid Spencer2007-04-161-0/+2
| | | | llvm-svn: 36123
* Regenerate.Reid Spencer2007-04-163-1207/+1049
| | | | llvm-svn: 36122
* For PR1328:Reid Spencer2007-04-161-0/+8
| | | | | | | | Use the new parameter on Function::getIntrinsicID to identify cases where a function is being called with an "llvm." name but it isn't actually an intrinsic. In such cases generate an error. llvm-svn: 36121
* For PR1328:Reid Spencer2007-04-161-3/+4
| | | | | | | | Don't assert everytime an intrinsic name isn't recognized. Instead, make the assert optional when callin getIntrinsicID(). This allows the assembler to handle invalid intrinsic names gracefully. llvm-svn: 36120
* Revert last patch. It was already fixed.Reid Spencer2007-04-161-6/+1
| | | | llvm-svn: 36102
* For PR1336:Reid Spencer2007-04-161-1/+6
| | | | | | | Fix a div-by-zero bug noticed by APInt. This fixes: test/Transforms/IndVarsSimplify/exit_value_tests.llx llvm-svn: 36099
* Tabs -> SpacesOwen Anderson2007-04-152-10/+10
| | | | llvm-svn: 36094
* Fix PR1335 and Transforms/Inline/2007-04-15-InlineEH.llChris Lattner2007-04-151-4/+5
| | | | llvm-svn: 36090
* Fix a nasty bug introduced when apint'ified. This fixesChris Lattner2007-04-151-4/+4
| | | | | | Transforms/IndVarsSimplify/exit_value_tests.llx llvm-svn: 36081
* Remove ImmediateDominator analysis. The same information can be obtained ↵Owen Anderson2007-04-155-186/+88
| | | | | | | | | | from DomTree. A lot of code for constructing ImmediateDominator is now folded into DomTree construction. This is part of the ongoing work for PR217. llvm-svn: 36063
* fix SimplifyLibCalls/IsDigit.llChris Lattner2007-04-151-1/+1
| | | | llvm-svn: 36047
* Extend store merging to support the 'if/then' version in addition to ↵Chris Lattner2007-04-151-26/+60
| | | | | | | | | | | | | | | | | | | | if/then/else. This sinks the two stores in this example into a single store in cond_next. In this case, it allows elimination of the load as well: store double 0.000000e+00, double* @s.3060 %tmp3 = fcmp ogt double %tmp1, 5.000000e-01 ; <i1> [#uses=1] br i1 %tmp3, label %cond_true, label %cond_next cond_true: ; preds = %entry store double 1.000000e+00, double* @s.3060 br label %cond_next cond_next: ; preds = %entry, %cond_true %tmp6 = load double* @s.3060 ; <double> [#uses=1] This implements Transforms/InstCombine/store-merge.ll:test2 llvm-svn: 36040
* refactor some code, no functionality change.Chris Lattner2007-04-151-58/+77
| | | | llvm-svn: 36037
* Fix some unsafe code. Also, tabs -> spaces.Owen Anderson2007-04-141-6/+6
| | | | llvm-svn: 36035
* Make ETForest depend on DomTree rather than IDom. This is the first stepOwen Anderson2007-04-141-8/+11
| | | | | | in the long process that will be fixing PR 217. llvm-svn: 36034
* fix long linesChris Lattner2007-04-146-18/+20
| | | | llvm-svn: 36031
* add a noteChris Lattner2007-04-141-0/+18
| | | | llvm-svn: 36028
* Implement Transforms/InstCombine/vec_extract_elt.ll, transforming:Chris Lattner2007-04-141-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | define i32 @test(float %f) { %tmp7 = insertelement <4 x float> undef, float %f, i32 0 %tmp17 = bitcast <4 x float> %tmp7 to <4 x i32> %tmp19 = extractelement <4 x i32> %tmp17, i32 0 ret i32 %tmp19 } into: define i32 @test(float %f) { %tmp19 = bitcast float %f to i32 ; <i32> [#uses=1] ret i32 %tmp19 } On PPC, this is the difference between: _test: mfspr r2, 256 oris r3, r2, 8192 mtspr 256, r3 stfs f1, -16(r1) addi r3, r1, -16 addi r4, r1, -32 lvx v2, 0, r3 stvx v2, 0, r4 lwz r3, -32(r1) mtspr 256, r2 blr and: _test: stfs f1, -4(r1) nop nop nop lwz r3, -4(r1) blr llvm-svn: 36025
* Implement InstCombine/vec_demanded_elts.ll:test2. This allows us to turnChris Lattner2007-04-141-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unsigned test(float f) { return _mm_cvtsi128_si32( (__m128i) _mm_set_ss( f*f )); } into: _test: movss 4(%esp), %xmm0 mulss %xmm0, %xmm0 movd %xmm0, %eax ret instead of: _test: movss 4(%esp), %xmm0 mulss %xmm0, %xmm0 xorps %xmm1, %xmm1 movss %xmm0, %xmm1 movd %xmm1, %eax ret GCC gets: _test: subl $28, %esp movss 32(%esp), %xmm0 mulss %xmm0, %xmm0 xorps %xmm1, %xmm1 movss %xmm0, %xmm1 movaps %xmm1, %xmm0 movd %xmm0, 12(%esp) movl 12(%esp), %eax addl $28, %esp ret llvm-svn: 36020
* avoid copying sets and vectors around.Chris Lattner2007-04-141-7/+6
| | | | llvm-svn: 36017
* Fix PR1329.Jeff Cohen2007-04-141-0/+28
| | | | llvm-svn: 36016
* disable switch lowering using shift/and. It still breaks ppc bootstrap forChris Lattner2007-04-141-0/+1
| | | | | | some reason. :( Will investigate. llvm-svn: 36011
* avoid iterator invalidation.Chris Lattner2007-04-141-2/+4
| | | | llvm-svn: 36002
* An even better fix.Jeff Cohen2007-04-141-3/+2
| | | | llvm-svn: 35998
* Fix recent regression that broke several llvm-tests.Jeff Cohen2007-04-141-0/+2
| | | | llvm-svn: 35996
* Fix PR1325: Case range optimization was performed in the case itAnton Korobeynikov2007-04-141-4/+2
| | | | | | shouldn't. Also fix some "latent" bug on 64-bit platforms llvm-svn: 35990
* disable shift/and lowering to work around PR1325 for now.Chris Lattner2007-04-141-1/+3
| | | | llvm-svn: 35985
* Implement a few missing xforms: printf("foo\n") -> puts. printf("x") -> putcharChris Lattner2007-04-141-9/+48
| | | | | | | | printf("") -> noop. Still need to do the xforms for fprintf. This implements Transforms/SimplifyLibCalls/Printf.ll llvm-svn: 35984
* in addition to merging, constantmerge should also delete trivially dead globals,Chris Lattner2007-04-141-1/+8
| | | | | | in order to clean up after simplifylibcalls. llvm-svn: 35982
* Implement PR1201 and test/Transforms/InstCombine/malloc-free-delete.llChris Lattner2007-04-141-8/+23
| | | | llvm-svn: 35981
* use an accessor to simplify code.Chris Lattner2007-04-141-15/+1
| | | | llvm-svn: 35979
* add GetElementPtrInst::hasAllZeroIndices, a long-overdue helper method.Chris Lattner2007-04-141-0/+16
| | | | | | Writing it twice in the same day was too much for me. llvm-svn: 35978
* We want the number of bits needed, not the power of 2.Reid Spencer2007-04-141-1/+1
| | | | llvm-svn: 35977
* Silence VC++ warning.Jeff Cohen2007-04-131-1/+1
| | | | llvm-svn: 35975
* Now that codegen prepare isn't defeating me, I can finally fix what I setChris Lattner2007-04-131-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | out to do! :) This fixes a problem where LSR would insert a bunch of code into each MBB that uses a particular subexpression (e.g. IV+base+C). The problem is that this code cannot be CSE'd back together if inserted into different blocks. This patch changes LSR to attempt to insert a single copy of this code and share it, allowing codegenprepare to duplicate the code if it can be sunk into various addressing modes. On CodeGen/ARM/lsr-code-insertion.ll, for example, this gives us code like: add r8, r0, r5 str r6, [r8, #+4] .. ble LBB1_4 @cond_next LBB1_3: @cond_true str r10, [r8, #+4] LBB1_4: @cond_next ... LBB1_5: @cond_true55 ldr r6, LCPI1_1 str r6, [r8, #+4] instead of: add r10, r0, r6 str r8, [r10, #+4] ... ble LBB1_4 @cond_next LBB1_3: @cond_true add r8, r0, r6 str r10, [r8, #+4] LBB1_4: @cond_next ... LBB1_5: @cond_true55 add r8, r0, r6 ldr r10, LCPI1_1 str r10, [r8, #+4] Besides being smaller and more efficient, this makes it immediately obvious that it is profitable to predicate LBB1_3 now :) llvm-svn: 35972
* Completely rewrite addressing-mode related sinking of code. In particular,Chris Lattner2007-04-131-341/+542
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this fixes problems where codegenprepare would sink expressions into load/stores that are not valid, and fixes cases where it would miss important valid ones. This fixes several serious codesize and perf issues, particularly on targets with complex addressing modes like arm and x86. For example, now we compile CodeGen/X86/isel-sink.ll to: _test: movl 8(%esp), %eax movl 4(%esp), %ecx cmpl $1233, %eax ja LBB1_2 #F LBB1_1: #T movl $4, (%ecx,%eax,4) movl $141, %eax ret LBB1_2: #F movl (%ecx,%eax,4), %eax ret instead of: _test: movl 8(%esp), %eax leal (,%eax,4), %ecx addl 4(%esp), %ecx cmpl $1233, %eax ja LBB1_2 #F LBB1_1: #T movl $4, (%ecx) movl $141, %eax ret LBB1_2: #F movl (%ecx), %eax ret llvm-svn: 35970
* Implement a getBitsNeeded method to determine how many bits are needed toReid Spencer2007-04-131-0/+37
| | | | | | represent a string in binary form by an APInt. llvm-svn: 35968
* Remove use of SlowOperationInformer.Devang Patel2007-04-131-3/+0
| | | | llvm-svn: 35967
* Undo previous check-in.Devang Patel2007-04-131-1/+1
| | | | llvm-svn: 35966
* Hello uses LLVMSupport.a (SlowerOperationInformer)Devang Patel2007-04-131-1/+1
| | | | llvm-svn: 35965
* Fix PR1323 : we haven't updated phi nodes in good manner :)Anton Korobeynikov2007-04-131-0/+1
| | | | llvm-svn: 35963
* arm has r+r*s and r+i addr modes, but no r+i+r*s addr modes.Chris Lattner2007-04-131-1/+5
| | | | llvm-svn: 35962
OpenPOWER on IntegriCloud