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* [InstCombine] simplify code for shuffle mask canonicalization; NFCSanjay Patel2019-11-251-6/+4
| | | | We never use the local 'Mask' before returning, so that was dead code.
* [InstCombine] remove dead code from shuffle mask canonicalization; NFCSanjay Patel2019-11-251-2/+2
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* [InstCombine] simplify loop for shuffle mask canonicalization; NFCSanjay Patel2019-11-251-4/+4
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* [AMDGPU] Fix function name in debug outputJay Foad2019-11-251-3/+3
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* [AIX][XCOFF] Generate undefined symbol in symbol table for external function ↵jasonliu2019-11-252-9/+47
| | | | | | | | | | | | | | | | call Summary: This patch sets up the infrastructure for 1. Associate MCSymbolXCOFF with an MCSectionXCOFF when it could not get implicitly associated. 2. Generate undefined symbols. The patch itself generates undefined symbol for external function call only. Generate undefined symbol for external global variable and external function descriptors will be handled in separate patch(s) after this is land. Differential Revision: https://reviews.llvm.org/D70443
* [DebugInfo] Avoid register coalesing unsoundly changing DBG_VALUE locationsJeremy Morse2019-11-251-2/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | This is a re-land of D56151 / r364515 with a completely new implementation. Once MIR code leaves SSA form and the liveness of a vreg is considered, DBG_VALUE insts are able to refer to non-live vregs, because their debug-uses do not contribute to liveness. This non-liveness becomes problematic for optimizations like register coalescing, as they can't ``see'' the debug uses in the liveness analyses. As a result registers get coalesced regardless of debug uses, and that can lead to invalid variable locations containing unexpected values. In the added test case, the first vreg operand of ADD32rr is merged with various copies of the vreg (great for performance), but a DBG_VALUE of the unmodified operand is blindly updated to the modified operand. This changes what value the variable will appear to have in a debugger. Fix this by changing any DBG_VALUE whose operand will be resurrected by register coalescing to be a $noreg DBG_VALUE, i.e. give the variable no location. This is an overapproximation as some coalesced locations are safe (others are not) -- an extra domination analysis would be required to work out which, and it would be better if we just don't generate non-live DBG_VALUEs. Differential Revision: https://reviews.llvm.org/D64630
* [ARM][MVE] Select vqnegAnna Welker2019-11-251-11/+19
| | | | | | | | Adds a pattern to ARMInstrMVE.td to use a VQNEG instruction if an equivalent multi-instruction construct is found. Differential Revision: https://reviews.llvm.org/D70491
* [DebugInfo@O2][Utils] Undef instead of delete dbg.values in helper funcOCHyams2019-11-251-15/+7
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Related bug: https://bugs.llvm.org/show_bug.cgi?id=40648 Static helper function rewriteDebugUsers in Local.cpp deletes dbg.value intrinsics when it cannot move or rewrite them, or salvage the deleted instruction's value. It should instead undef them in this case. This patch fixes that and I've added a test which covers the failing test case in bz40648. I've updated the unit test Local.ReplaceAllDbgUsesWith to check for this behaviour (and fixed a typo in the test which would cause the old test to always pass). Reviewers: aprantl, vsk, djtodoro, probinson Reviewed By: vsk Subscribers: hiraditya, llvm-commits Tags: #debug-info, #llvm Differential Revision: https://reviews.llvm.org/D70604
* [AVR] Fix endianness handling in AVR MCserge_sans_paille2019-11-251-5/+3
| | | | Differential Revision: https://reviews.llvm.org/D67926
* [yaml2obj/obj2yaml] - Add support for SHT_LLVM_DEPENDENT_LIBRARIES sections.Georgii Rymar2019-11-252-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | This section contains strings specifying libraries to be added to the link by the linker. The strings are encoded as standard null-terminated UTF-8 strings. This patch adds a way to describe and dump SHT_LLVM_DEPENDENT_LIBRARIES sections. I introduced a new YAMLFlowString type here. That used to teach obj2yaml to dump them like: ``` Libraries: [ foo, bar ] ``` instead of the following (if StringRef would be used): ``` Libraries: - foo - bar ``` Differential revision: https://reviews.llvm.org/D70598
* Revert "[PowerPC] combine rlwinm+rlwinm to rlwinm"czhengsz2019-11-241-100/+0
| | | | This reverts commit 29f6f9b2b2bfecccf903738e2f5a0cd0a70fce31.
* Recommit f0c2a5a "[LV] Generalize conditions for sinking instrs for first ↵Florian Hahn2019-11-242-14/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | order recurrences." This version contains 2 fixes for reported issues: 1. Make sure we do not try to sink terminator instructions. 2. Make sure we bail out, if we try to sink an instruction that needs to stay in place for another recurrence. Original message: If the recurrence PHI node has a single user, we can sink any instruction without side effects, given that all users are dominated by the instruction computing the incoming value of the next iteration ('Previous'). We can sink instructions that may cause traps, because that only causes the trap to occur later, but not on any new paths. With the relaxed check, we also have to make sure that we do not have a direct cycle (meaning PHI user == 'Previous), which indicates a reduction relation, which potentially gets missed by ReductionDescriptor. As follow-ups, we can also sink stores, iff they do not alias with other instructions we move them across and we could also support sinking chains of instructions and multiple users of the PHI. Fixes PR43398. Reviewers: hsaito, dcaballe, Ayal, rengolin Reviewed By: Ayal Differential Revision: https://reviews.llvm.org/D69228
* [LoopInterchange] Adjust assertions when updating successors.Florian Hahn2019-11-241-19/+35
| | | | | | | | | | | Currently the assertion in updateSuccessor is overly strict in some cases and overly relaxed in other cases. For branches to the inner and outer loop preheader it is too strict, because they can either be unconditional branches or conditional branches with duplicate targets. Both cases are fine and we can allow updating multiple successors. On the other hand, we have to at least update one successor. This patch adds such an assertion.
* [InstCombine] remove identity shuffle simplification for mask with undefsSanjay Patel2019-11-242-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | And simultaneously enhance SimplifyDemandedVectorElts() to rcognize that pattern. That preserves some of the old optimizations in IR. Given a shuffle that includes undef elements in an otherwise identity mask like: define <4 x float> @shuffle(<4 x float> %arg) { %shuf = shufflevector <4 x float> %arg, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3> ret <4 x float> %shuf } We were simplifying that to the input operand. But as discussed in PR43958: https://bugs.llvm.org/show_bug.cgi?id=43958 ...that means that per-vector-element poison that would be stopped by the shuffle can now leak to the result. Also note that we still have (and there are tests for) the same transform with no undef elements in the mask (a fully-defined identity mask). I don't think there's any controversy about that case - it's a valid transform under any interpretation of shufflevector/undef/poison. Looking at a few of the diffs into codegen, I don't see any difference in final asm. So depending on your perspective, that's good (no real loss of optimization power) or bad (poison exists in the DAG, so we only partially fixed the bug). Differential Revision: https://reviews.llvm.org/D70246
* [PowerPC] Spill CR LT bits on P9 using setbAmy Kwan2019-11-241-0/+15
| | | | | | | | | | | | | | | | This patch aims to spill CR[0-7]LT bits on POWER9 using the setb instruction. The sequence on P9 to spill these bits will be: setb %reg, %CRREG stw %reg, $FI Instead of the typical sequence: mfocrf %reg, %CRREG rlwinm %reg1, %reg, $SH, 0, 0 stw %reg1, $FI Differential Revision: https://reviews.llvm.org/D68443
* [ModuloSchedule] Fix a bug in experimental expanderThomas Raoux2019-11-231-14/+62
| | | | | | | | | Fix two problems that popped up after my last patch. One is that the stiching of prologue/epilogue can be wrong when reading a value from a previsou stage. Also changed how we duplicate phi instructions to avoid generating extra phi that we delete later. Differential Revision: https://reviews.llvm.org/D70213
* [pdbutil] Fixed -Wdeprecated-copy in DbiModuleDescriptorDávid Bolvanský2019-11-231-5/+0
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* Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-232-2/+16
| | | | Fixed hashtable copy ctor.
* Revert 'Fixed -Wdeprecated-copy warnings. NFCI.'Dávid Bolvanský2019-11-232-16/+2
| | | | pdbutil's test is failing.
* Fixed -Wdeprecated-copy warnings. NFCI.Dávid Bolvanský2019-11-232-2/+16
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* Revert "[InlineCost] Fix infinite loop in indirect call evaluation"Ehud Katz2019-11-231-91/+84
| | | | | | | This reverts commit 854e956219e78cb8d7ef3b021d7be6b5d6b6af04. It broke tests: Transforms/Inline/redundant-loads.ll Transforms/SampleProfile/inline-callee-update.ll
* [NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOpDavid Tellenbach2019-11-231-1/+1
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* AMDGPU: Handle waitcnt overflowAustin Kerbow2019-11-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | Summary: The waitcnt pass can overflow the counters when the number of outstanding events for a type exceed the capacity of the counter. This can lead to inefficient insertion of waitcnts, or to waitcnt instructions with max values for each type. The last situation can cause an instruction which when disassembled appears to be an illegal waitcnt without an operand. In these cases we should add a wait for the 'counter maximum' - 1, and update the waitcnt brackets accordingly. Reviewers: rampitec, arsenm Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70418
* [InlineCost] Fix infinite loop in indirect call evaluationEhud Katz2019-11-231-84/+91
| | | | | | | | | | | | | | | Currently every time we encounter an indirect call of a known function, we try to evaluate the inline cost of that function. In case of a recursion, that evaluation never stops. The solution presented is to evaluate only the indirect call of the function, while any further indirect calls (of a known function) will be treated just as direct function calls, which, actually, never tries to evaluate the call. Fixes PR35469. Differential Revision: https://reviews.llvm.org/D69349
* Recommit "[DWARF] Support for loclist.dwo section in llvm and llvm-dwarfdump."Sourabh Singh Tomar2019-11-235-26/+78
| | | | | | | | | | | The original commit message follows. This patch adds support for debug_loclists.dwo section in llvm and llvm-dwarfdump. Also Fixes PR43622, PR43623. Reviewers: dblaikie, probinson, labath, aprantl, jini.susan.george Differential Revision: https://reviews.llvm.org/D69462
* Revert "[DWARF] Support for loclist.dwo section in llvm and llvm-dwarfdump."Sourabh Singh Tomar2019-11-234-77/+26
| | | | | | This reverts commit 81b0a3284af1dcef26e56b0de9fd74002083c471. Will Re-apply, with updated Differtial Revision, for automatic closure of Phabricator review.
* [X86][SSE] Split off generic isLaneCrossingShuffleMask helper. NFC.Simon Pilgrim2019-11-231-3/+14
| | | | Avoid MVT dependency which will be needed in a future patch.
* [PhiValues] Remove redundant map searchesEhud Katz2019-11-231-24/+38
| | | | | | | | | Remove redundant map searches. For example, every call to "operator[]" is actually translated to a "find" call, and 2 consecutive calls to the operator, without changing the map in-between, is just redundant, and inefficient. Differential Revision: https://reviews.llvm.org/D69337
* [DWARF] Support for loclist.dwo section in llvm and llvm-dwarfdump.Sourabh Singh Tomar2019-11-234-26/+77
| | | | | | | | | This patch adds support for debug_loclists.dwo section in llvm and llvm-dwarfdump. Also Fixes PR43622, PR43623. Reviewers: dblaikie, probinson, labath, aprantl, jini.susan.george https://reviews.llvm.org/D69462
* [IR] Move global_objects and global_values out of line, NFCReid Kleckner2019-11-221-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | This saves 2.4% of CPU time compiling opt, according to ClangBuildAnalyzer. These helpers being inlined in the header was triggering the instantiation of concat_iterator in every TU using Module.h (~1118 TUs): https://reviews.llvm.org/P8171$35 **** Templates that took longest to instantiate: 76187 ms: llvm::AnalysisManager<llvm::Function>::getResult<llvm::TargetLibrary... (396 times, avg 192 ms) 73609 ms: llvm::AnalysisManager<llvm::Function>::getResultImpl (420 times, avg 175 ms) 49657 ms: llvm::detail::concat_range<llvm::GlobalValue, llvm::iterator_range<l... (1118 times, avg 44 ms) 49376 ms: llvm::detail::concat_range<const llvm::GlobalValue, llvm::iterator_r... (1118 times, avg 44 ms) 48167 ms: llvm::iterator_range<llvm::concat_iterator<llvm::GlobalValue, llvm::... (1118 times, avg 43 ms) 48125 ms: llvm::iterator_range<llvm::concat_iterator<const llvm::GlobalValue, ... (1118 times, avg 43 ms) 48061 ms: llvm::concat_iterator<llvm::GlobalValue, llvm::ilist_iterator<llvm::... (1118 times, avg 42 ms) 48014 ms: llvm::concat_iterator<const llvm::GlobalValue, llvm::ilist_iterator<... (1118 times, avg 42 ms) ... I haven't measured, but I don't think these helpers are performance critical. The iterator advance call can still be inlined, which is what matters for performance. Remove global_(objects|values)_(begin|end), since they were dead and would have to be out of line anyway.
* [Remarks] Allow empty temporary remark filesFrancis Visoiu Mistrih2019-11-221-0/+5
| | | | | | | When parsing bitstream remarks, allow external remark files to be empty, which means there are no remarks to be parsed. In the same way, dsymutil should not produce a remark file.
* [InstCombine] Fix call guard difference with dbgDavide Italiano2019-11-221-4/+4
| | | | | | Patch by Chris Ye! Differential Revision: https://reviews.llvm.org/D68004
* [CodeMoverUtils] Added an API to check if an instruction can be safelyTsang Whitney W.H2019-11-223-0/+192
| | | | | | | | | | | | | | | | | | | moved before another instruction. Summary:Added an API to check if an instruction can be safely moved before another instruction. In future PRs, we will like to add support of moving instructions between blocks that are not control flow equivalent, and add other APIs to enhance usability, e.g. moving basic blocks, moving list of instructions... Loop Fusion will be its first user. When there is intervening code in between two loops, fusion is currently unable to fuse them. Loop Fusion can use this utility to check if the intervening code can be safely moved before or after the two loops, and move them, then it can successfully fuse them. Reviewer:kbarton,jdoerfert,Meinersbur,bmahjour,etiotto Reviewed By:bmahjour Subscribers:mgorny,hiraditya,llvm-commits Tag:LLVM Differential Revision:https://reviews.llvm.org/D70049
* [AArch64] Add the pipeline model for Exynos M5Evandro Menezes2019-11-222-1/+1014
| | | | Add the scheduling and cost models for Exynos M5.
* Slightly speculative buildbot fix for issue reported in 8293f74 commit threadPhilip Reames2019-11-221-1/+4
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* Reinstate MSan suppression of PR24578.Evgenii Stepanov2019-11-222-2/+6
| | | | | | | | | | | | | | | | | | | Summary: Revert "Rollback of commit "Repress sanitization on User dtor."" There is no point in keeping an active MSan error in the codebase. PR24578 tracks the actual UB in LLVM code; this change enables testing of LLVM with MSAN + -fsanitize-memory-use-after-dtor. This reverts commit 21c1bc46aee2b69c2c48db8e961f0ce8394f21e1. Reviewers: vitalybuka Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70611
* [APFloat] Fix subtraction of subnormal numbersEhud Katz2019-11-221-7/+4
| | | | | | | | Fix incorrect determination of the bigger number out of the two subtracted, while subnormal numbers are involved. Fixes PR44010. Differential Revision: https://reviews.llvm.org/D69772
* [SLP] Enhance SLPVectorizer to vectorize vector aggregateAnton Afanasyev2019-11-221-6/+27
| | | | | | | | | | | | | | | | | Summary: Vector aggregate is homogeneous aggregate of vectors like `{ <2 x float>, <2 x float> }`. This patch allows `findBuildAggregate()` to consider vector aggregates as well as scalar ones. For instance, `{ <2 x float>, <2 x float> }` maps to `<4 x float>`. Fixes vector part of llvm.org/PR42022 Reviewers: RKSimon Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70068
* [WebAssembly][SelectionDAG] Remove unused WebAssemblyDAGToDAGISel::ForCodeSize.Hiroshi Yamauchi2019-11-221-4/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: This follows from the discussion at D70095. D70095 moves hasOptSize calls into SelectionDAG::shouldOptForSize to allow querying size optimization conditions together with profile guided size optimization. Since it appears that size optimizations for WebAssembly SelectionDAG haven't been implemented yet and thus ForCodeSize is unused, and it would not make a lot of sense to call shouldOptForSize here as the necessary profile data like PSI/BFI aren't available at this point, it seems good and less confusing to remove this for now and use shouldOptForSize when they are implemented in the future. Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70567
* [JumpThreading] NFC: Don't cache F.hasProfileData()Kazu Hirata2019-11-221-3/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: With this patch, we no longer cache F.hasProfileData(). We simply call the function again. I'm doing this because: - JumpThreadingPass also has a member variable named HasProfileData, which is very confusing, - the function is very lightweight, and - this patch makes JumpThreading::runOnFunction more consistent with JumpThreadingPass::run. Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70602
* [JumpThreading] Use profile data even with the new pass managerKazu Hirata2019-11-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Without this patch, the jump threading pass ignores profiling data whenever we invoke the pass with the new pass manager. Specifically, JumpThreadingPass::run calls runImpl with class variable HasProfileData always set to false. In turn, runImpl sets HasProfileData to false again: HasProfileData = HasProfileData_; In the end, we don't use profiling data at all with the new pass manager. This patch fixes the problem by passing F.hasProfileData() to runImpl. The bug appears to have been introduced at: https://reviews.llvm.org/D41461 which removed local variable HasProfileData in JumpThreadingPass::run even though there was one more use left in the same function. As a result, the remaining use ended referring to the class variable instead. Note that F.hasProfileData is an extremely lightweight function, so I don't see the need to cache its result. Once this patch is approved, I'm planning to stop caching the result of F.hasProfileData in runOnFunction. Reviewers: wmi, eli.friedman Subscribers: hiraditya, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70509
* [BPF] Fix a recursion bug in BPF Peephole ZEXT optimizationYonghong Song2019-11-221-2/+13
| | | | | | | | | | | | | | | | | | | Commit a0841dfe8594 ("[BPF] Fix a bug in peephole optimization") fixed a bug in peephole optimization. Recursion is introduced to handle COPY and PHI instructions. Unfortunately, multiple PHI instructions may form a cycle and this will cause infinite recursion, eventual segfault. For Commit a0841dfe8594, I indeed tried a few loops to ensure that I won't see the recursion, but I did not try with complex control flows, which, as demonstrated with the test case in this patch, may introduce PHI cycles. This patch fixed the issue by introducing a set to remember visited PHI instructions. This way, cycles can be properly detected and handled. Differential Revision: https://reviews.llvm.org/D70586
* [XCOFF][AIX] Read-only data section object file generationjasonliu2019-11-221-1/+6
| | | | | | | | | | Summary: This patch is a follow up on read-only assembly patch D70182. It intends to enable object file generation for the read-only data section on AIX. Reviewers: DiggerLin, daltenty Differential Revision: https://reviews.llvm.org/D70455
* Reland "[DAGCombiner] Allow zextended load combines."Clement Courbet2019-11-221-17/+59
| | | | Check that the generated type is simple.
* [WIP][Attributor] AAReachability AttributePankaj Gode2019-11-221-0/+30
| | | | | | | | | | | | | | | | | Summary: Working towards Johannes's suggestion for fixme, in Attributor's Noalias attribute deduction. (ii) Check whether the value is captured in the scope using AANoCapture. FIXME: This is conservative though, it is better to look at CFG and // check only uses possibly executed before this call site. A Reachability abstract attribute answers the question "does execution at point A potentially reach point B". If this question is answered with false for all other uses of the value that might be captured, we know it is not *yet* captured and can continue with the noalias deduction. Currently, information AAReachability provides is completely pessimistic. Reviewers: jdoerfert Reviewed By: jdoerfert Subscribers: uenoku, sstefan1, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D70233
* [Codegen] TargetLowering::prepareUREMEqFold(): `x u% C1 ==/!= C2` (PR35479)Roman Lebedev2019-11-221-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The current lowering is: ``` Name: (X % C1) == C2 -> X * C3 <= C4 || false Pre: (C2 == 0 || C1 u<= C2) && (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %C4_fixed = select i1 %is_tautologically_false, i8 -1, i8 %C4 %res = icmp ule i8 %n3, %C4_fixed %r = xor i1 %res, %is_tautologically_false ``` https://rise4fun.com/Alive/2xC https://rise4fun.com/Alive/jpb5 However, we can support non-tautological cases `C1 u> C2` too. Said handling consists of two parts: * `C2 u<= (-1 %u C1)`. It just works. We only have to change `(X % C1) == C2` into `((X - C2) % C1) == 0` ``` Name: (X % C1) == C2 -> (X - C2) * C3 <= C4 iff C2 u<= (-1 %u C1) Pre: (C1 u>> countTrailingZeros(C1)) * C3 == 1 && C2 u<= (-1 %u C1) %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = (-1 /u C1) %n0 = sub i8 %x, C2 %n1 = mul i8 %n0, C3 %n2 = lshr i8 %n1, countTrailingZeros(C1) ; rotate right %n3 = shl i8 %n1, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n4 = or i8 %n2, %n3 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %C4_fixed = select i1 %is_tautologically_false, i8 -1, i8 %C4 %res = icmp ule i8 %n4, %C4_fixed %r = xor i1 %res, %is_tautologically_false ``` https://rise4fun.com/Alive/m4P https://rise4fun.com/Alive/SKrx * `C2 u> (-1 %u C1)`. We also have to change `(X % C1) == C2` into `((X - C2) % C1) == 0`, and we have to decrement C4: ``` Name: (X % C1) == C2 -> (X - C2) * C3 <= C4 iff C2 u> (-1 %u C1) Pre: (C1 u>> countTrailingZeros(C1)) * C3 == 1 && C2 u> (-1 %u C1) %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = (-1 /u C1)-1 %n0 = sub i8 %x, C2 %n1 = mul i8 %n0, C3 %n2 = lshr i8 %n1, countTrailingZeros(C1) ; rotate right %n3 = shl i8 %n1, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n4 = or i8 %n2, %n3 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %C4_fixed = select i1 %is_tautologically_false, i8 -1, i8 %C4 %res = icmp ule i8 %n4, %C4_fixed %r = xor i1 %res, %is_tautologically_false ``` https://rise4fun.com/Alive/d40 https://rise4fun.com/Alive/8cF I believe this concludes `x u% C1 ==/!= C2` lowering. In fact, clang is may now be better in this regard than gcc: as it can be seen from `@t32_6_4` test, we do lower `x % 6 == 4` via this pattern, while gcc does not: https://godbolt.org/z/XNU2z9 And all the general alive proofs say this is legal. And manual checking agrees: https://rise4fun.com/Alive/WA2 Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=35479 | PR35479 ]]. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: nick, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70053
* [Codegen] TargetLowering::prepareUREMEqFold(): `x u% C1 ==/!= C2` with ↵Roman Lebedev2019-11-221-25/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tautological C1 u<= C2 (PR35479) Summary: This is a preparatory cleanup before i add more of this fold to deal with comparisons with non-zero. In essence, the current lowering is: ``` Name: (X % C1) == 0 -> X * C3 <= C4 Pre: (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, 0 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %r = icmp ule i8 %n3, %C4 ``` https://rise4fun.com/Alive/oqd It kinda just works, really no weird edge-cases. But it isn't all that great for when comparing with non-zero. In particular, given `(X % C1) == C2`, there will be problems in the always-false tautological case where `C2 u>= C1`: https://rise4fun.com/Alive/pH3 That case is tautological, always-false: ``` Name: (X % Y) u>= Y %o0 = urem i8 %x, %y %r = icmp uge i8 %o0, %y => %r = false ``` https://rise4fun.com/Alive/ofu While we can't/shouldn't get such tautological case normally, we do deal with non-splat vectors, so unless we want to give up in this case, we need to fixup/short-circuit such lanes. There are two lowering variants: 1. We can blend between whatever computed result and the correct tautological result ``` Name: (X % C1) == C2 -> X * C3 <= C4 || false Pre: (C2 == 0 || C1 u<= C2) && (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %res = icmp ule i8 %n3, %C4 %r = select i1 %is_tautologically_false, i1 0, i1 %res ``` https://rise4fun.com/Alive/PjT5 https://rise4fun.com/Alive/1KV 2. We can invert the comparison result ``` Name: (X % C1) == C2 -> X * C3 <= C4 || false Pre: (C2 == 0 || C1 u<= C2) && (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %C4_fixed = select i1 %is_tautologically_false, i8 -1, i8 %C4 %res = icmp ule i8 %n3, %C4_fixed %r = xor i1 %res, %is_tautologically_false ``` https://rise4fun.com/Alive/2xC https://rise4fun.com/Alive/jpb5 3. We can expand into `and`/`or`: https://rise4fun.com/Alive/WGn https://rise4fun.com/Alive/lcb5 Blend-one is likely better since we avoid having to load the replacement from constant pool. `xor` is second best since it's still pretty general. I'm not adding `and`/`or` variants. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: nick, hiraditya, xbolva00, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70051
* Test commit.Pankaj Gode2019-11-221-1/+1
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* [DWARFVerifier] Use the new location list apiPavel Labath2019-11-223-79/+25
| | | | | | | | | | | | | | | | | | Summary: Instead of going to the debug_loc section directly, use new DWARFDie::getLocations instead. This means that the code will now automatically support debug_loclists sections. This is the last usage of the old debug_loc methods, and they can now be removed. Reviewers: dblaikie, JDevlieghere, aprantl, SouraVX Subscribers: hiraditya, probinson, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70534
* [PowerPC] Implement the vector extend sign instruction pattern matchQingShan Zhang2019-11-222-0/+14
| | | | | | | Power9 has instructions to implement the semantics of SIGN_EXTEND_INREG for vector type. Mark it as legal and add the match pattern. Differential Revision: https://reviews.llvm.org/D69601
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