summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* This patch adds aliases for Mips sub instruction with immediate operands. ↵Vladimir Medic2013-10-012-2/+38
| | | | | | Corresponding test cases are added. llvm-svn: 191734
* AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-011-0/+5
| | | | llvm-svn: 191733
* Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
| | | | llvm-svn: 191732
* Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-012-20/+0
| | | | llvm-svn: 191731
* BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
| | | | llvm-svn: 191728
* SelectionDAG: Clarify comments from r191600Tom Stellard2013-10-011-2/+2
| | | | llvm-svn: 191724
* Adding multiple module support for MCJIT.Andrew Kaylor2013-10-015-99/+366
| | | | | | | | Tests to follow. PIC with small code model and EH frame handling will not work with multiple modules. There are also some rough edges to be smoothed out for remote target support. llvm-svn: 191722
* Add the DW_AT_GNU_ranges_base attribute if we've emitted any rangesEric Christopher2013-10-011-2/+11
| | | | | | into the debug_ranges section. llvm-svn: 191721
* Update comments.Eric Christopher2013-10-011-2/+2
| | | | llvm-svn: 191720
* Fix code duplicationMatt Arsenault2013-10-011-21/+10
| | | | llvm-svn: 191716
* Forgot to add a break statement.Preston Gurd2013-09-301-0/+1
| | | | llvm-svn: 191715
* Reuse variableMatt Arsenault2013-09-301-1/+1
| | | | llvm-svn: 191712
* The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddressPreston Gurd2013-09-301-0/+8
| | | | | | | | | | | on ADD16rr opcodes, if src1 != src, since that would cause convertToThreeAddress to try to create a virtual register. This is not permitted after register allocation, which is when the X86FixupLEAs pass runs. This patch fixes PR16785. llvm-svn: 191711
* The DW_AT_GNU_pubnames/pubtypes attributes are actually formEric Christopher2013-09-302-6/+58
| | | | | | | SEC_OFFSET from the beginning of the section so go ahead and emit a label at the beginning of each one. llvm-svn: 191710
* Fix getOrInsertGlobal dropping the address space.Matt Arsenault2013-09-301-2/+4
| | | | | | | | Currently it will insert an illegal bitcast. Arguably, the address space argument should be added for the creation case. llvm-svn: 191702
* Use right address space size in InstCombineComparesMatt Arsenault2013-09-301-3/+6
| | | | | | | The test's output doesn't change, but this ensures this is actually hit with a different address space. llvm-svn: 191701
* Constant fold ptrtoint + compare with address spacesMatt Arsenault2013-09-301-1/+1
| | | | llvm-svn: 191699
* Debug Info: constify and rename from generateRef to getRef.Manman Ren2013-09-302-9/+9
| | | | | | No functionality change. llvm-svn: 191696
* llvm-c: use typedef for function pointersAnders Waldenborg2013-09-301-16/+8
| | | | | | | | This makes it consistent with other function pointers used in llvm-c Differential Revision: http://llvm-reviews.chandlerc.com/D1712 llvm-svn: 191693
* [mips][msa] Direct Object Emission for I8 instructions.Jack Carter2013-09-302-28/+39
| | | | | | | | | This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
* [mips][msa] Direct Object Emission for I5 instructions.Jack Carter2013-09-302-49/+64
| | | | | | | | | This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
| | | | | | | | Fix some LLVM Coding Standards violations. No changes in functionality. llvm-svn: 191686
* [mips][msa] Direct Object Emission for 2R instructions.Jack Carter2013-09-302-16/+21
| | | | | | | | | This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
* [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPRJack Carter2013-09-302-15/+26
| | | | | | | | and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
* Move command line options to the users of libLTO. Fixes --enable-shared build.Rafael Espindola2013-09-302-151/+53
| | | | | | Patch by Richard Sandiford. llvm-svn: 191680
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be ↵Tilmann Scheller2013-09-301-4/+19
| | | | | | | | | | different from the destination registers. See ARM ARM A8.8.72. Violating this constraint results in unpredictable behavior. llvm-svn: 191678
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
| | | | | | Those writes really need two/three uops. llvm-svn: 191677
* BoundsChecking: Fix refacto.Benjamin Kramer2013-09-301-0/+1
| | | | llvm-svn: 191676
* Convert manual insert point restores to the new RAII object.Benjamin Kramer2013-09-304-60/+18
| | | | llvm-svn: 191675
* InstCombine: Replace manual fast math flag copying with the new IRBuilder ↵Benjamin Kramer2013-09-301-22/+20
| | | | | | | | | RAII helper. Defines away the issue where cast<Instruction> would fail because constant folding happened. Also slightly cleaner. llvm-svn: 191674
* IRBuilder: Add RAII objects to reset insertion points or fast math flags.Benjamin Kramer2013-09-301-21/+1
| | | | | | | | Inspired by the object from the SLPVectorizer. This found a minor bug in the debug loc restoration in the vectorizer where the location of a following instruction was attached instead of the location from the original instruction. llvm-svn: 191673
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-307-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Fix a bug in InstCombine where it attempted to cast a Value* to an Instruction*Joey Gouly2013-09-301-2/+2
| | | | | | | | | when it was actually a Constant*. There are quite a few other casts to Instruction that might have the same problem, but this is the only one I have a test case for. llvm-svn: 191668
* [SystemZ] Revert r191661: Add definitions of LFH and STFHRichard Sandiford2013-09-301-4/+0
| | | | | | | | For some reason, adding definitions for these load and store instructions changed whether some of the build bots matched comparisons as signed or unsigned. llvm-svn: 191663
* [SystemZ] Add definitions of LFH and STFHRichard Sandiford2013-09-301-0/+4
| | | | llvm-svn: 191661
* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-306-14/+38
| | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. llvm-svn: 191660
* [SystemZ] Rename subregs and add subreg_h32Richard Sandiford2013-09-309-60/+61
| | | | | | | | | | | | | Use subreg_hNN and subreg_lNN for the high and low NN bits of a register. List the low registers first, so that subreg_l32 also means the low 32 bits of a 128-bit register. Floats are stored in the upper 32 bits of a 64-bit register, so they should use subreg_h32 rather than subreg_l32. No behavioral change intended. llvm-svn: 191659
* [SystemZ] Add change missing from previous commitRichard Sandiford2013-09-301-1/+1
| | | | llvm-svn: 191656
* [SystemZ] Rename 32-bit GPR registersRichard Sandiford2013-09-306-20/+20
| | | | | | | | I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. llvm-svn: 191655
* Various x86 disassembler fixes.Craig Topper2013-09-303-47/+12
| | | | | | | | | | | Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649
* ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a ↵Benjamin Kramer2013-09-291-5/+7
| | | | | | | | cyclic GEP. Those can occur in dead code. PR17402. llvm-svn: 191644
* Deallocate type units when destroying a DWARFContext.Benjamin Kramer2013-09-291-0/+1
| | | | llvm-svn: 191637
* Allocate AtomicSDNode operands in SelectionDAG's allocator to stop leakage.Benjamin Kramer2013-09-291-2/+10
| | | | | | | SDNode destructors are never called. As an optimization use AtomicSDNode's internal storage if we have a small number of operands. llvm-svn: 191636
* Change type of XOP flag in code emitters to a bool. Remove a some unneeded ↵Craig Topper2013-09-292-14/+8
| | | | | | cases from switch. llvm-svn: 191632
* Add comments for XOPA map introduced with TBM instructions.aCraig Topper2013-09-292-2/+4
| | | | llvm-svn: 191630
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-2811-16/+16
| | | | llvm-svn: 191611
* Fix spelling intruction -> instruction.Robert Wilhelm2013-09-286-7/+7
| | | | llvm-svn: 191610
* SelectionDAG: Silence unused variable warning on release buildsTom Stellard2013-09-281-0/+1
| | | | llvm-svn: 191604
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-283-44/+40
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-282-17/+49
| | | | | | | | | | | SelectionDAG will now attempt to inverse an illegal conditon in order to find a legal one and if that doesn't work, it will attempt to swap the operands using the inverted condition. There are no new test cases for this, but a nubmer of the existing R600 tests hit this path. llvm-svn: 191602
OpenPOWER on IntegriCloud