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* Add a new AddToWorkList method, start using itChris Lattner2006-03-011-57/+63
| | | | llvm-svn: 26441
* Pull shifts by a constant through multiplies (a form of reassociation),Chris Lattner2006-03-011-0/+27
| | | | | | implementing Regression/CodeGen/X86/mul-shift-reassoc.ll llvm-svn: 26440
* Vector op lowering.Evan Cheng2006-03-012-6/+35
| | | | llvm-svn: 26438
* Vector ops lowering.Evan Cheng2006-03-013-50/+76
| | | | llvm-svn: 26436
* New type v2f32.Evan Cheng2006-03-011-2/+3
| | | | llvm-svn: 26435
* - Added VConstant as an abstract version of ConstantVec.Evan Cheng2006-03-011-12/+19
| | | | | | | - All abstrct vector nodes must have # of elements and element type as their first two operands. llvm-svn: 26432
* Another entry.Evan Cheng2006-02-281-0/+16
| | | | llvm-svn: 26430
* Don't match x << 1 to LEAL. It's better to emit x + x.Evan Cheng2006-02-281-1/+4
| | | | llvm-svn: 26429
* Add const, volatile, restrict support.Jim Laskey2006-02-282-5/+67
| | | | | | Add array of debug descriptor support. llvm-svn: 26428
* Fix a regression in a patch from a couple of days ago. This fixesChris Lattner2006-02-281-1/+3
| | | | | | Transforms/InstCombine/2006-02-28-Crash.ll llvm-svn: 26427
* Add a subtarget feature for the stfiwx instruction. I know the G5 has it,Chris Lattner2006-02-282-2/+6
| | | | | | | but I don't know what other PPC impls do. If someone could update the proc table, I would appreciate it :) llvm-svn: 26421
* Compile:Chris Lattner2006-02-281-10/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | unsigned foo4(unsigned short *P) { return *P & 255; } unsigned foo5(short *P) { return *P & 255; } to: _foo4: lbz r3,1(r3) blr _foo5: lbz r3,1(r3) blr not: _foo4: lhz r2, 0(r3) rlwinm r3, r2, 0, 24, 31 blr _foo5: lhz r2, 0(r3) rlwinm r3, r2, 0, 24, 31 blr llvm-svn: 26419
* remove implemented itemChris Lattner2006-02-281-17/+0
| | | | llvm-svn: 26418
* Fold "and (LOAD P), 255" -> zextload. This allows us to compile:Chris Lattner2006-02-281-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | unsigned foo3(unsigned *P) { return *P & 255; } as: _foo3: lbz r3, 3(r3) blr instead of: _foo3: lwz r2, 0(r3) rlwinm r3, r2, 0, 24, 31 blr and: unsigned short foo2(float a) { return a; } as: _foo2: fctiwz f0, f1 stfd f0, -8(r1) lhz r3, -2(r1) blr instead of: _foo2: fctiwz f0, f1 stfd f0, -8(r1) lwz r2, -4(r1) rlwinm r3, r2, 0, 16, 31 blr llvm-svn: 26417
* fold (sra (sra x, c1), c2) -> (sra x, c1+c2)Chris Lattner2006-02-281-3/+11
| | | | llvm-svn: 26416
* Implement rem.ll:test[7-9] and PR712Chris Lattner2006-02-281-6/+22
| | | | llvm-svn: 26415
* Simplify some code now that the RHS of a rem can't be 0Chris Lattner2006-02-281-8/+6
| | | | llvm-svn: 26413
* Rearrange some code, fold "rem X, 0", implementing rem.ll:test6Chris Lattner2006-02-281-38/+39
| | | | llvm-svn: 26411
* Add support for output memory constraints.Chris Lattner2006-02-271-7/+38
| | | | llvm-svn: 26410
* Qualify dwarf namespace inside llvm namespace.Jim Laskey2006-02-272-2/+5
| | | | llvm-svn: 26409
* readme updatesNate Begeman2006-02-271-21/+26
| | | | llvm-svn: 26405
* Partial enabling of functions.Jim Laskey2006-02-271-1/+1
| | | | llvm-svn: 26404
* Don't print constant initializers, they may span lines now.Chris Lattner2006-02-271-2/+0
| | | | llvm-svn: 26403
* Supporting multiple compile units.Jim Laskey2006-02-271-136/+185
| | | | llvm-svn: 26402
* Re-orging file.Jim Laskey2006-02-272-556/+929
| | | | llvm-svn: 26401
* Pretty print large struct constants.Jim Laskey2006-02-271-1/+10
| | | | llvm-svn: 26400
* Removed dependency on how operands are printed (want multi-line.)Jim Laskey2006-02-271-9/+3
| | | | llvm-svn: 26399
* Merge two almost-identical pieces of code.Chris Lattner2006-02-271-46/+42
| | | | | | | | | | | | | | | Make this code more powerful by using ComputeMaskedBits instead of looking for an AND operand. This lets us fold this: int %test23(int %a) { %tmp.1 = and int %a, 1 %tmp.2 = seteq int %tmp.1, 0 %tmp.3 = cast bool %tmp.2 to int ;; xor tmp1, 1 ret int %tmp.3 } into: xor (and a, 1), 1 llvm-svn: 26396
* Fold (A^B) == A -> B == 0Chris Lattner2006-02-271-0/+26
| | | | | | and (A-B) == A -> B == 0 llvm-svn: 26394
* Implement bit propagation through sub nodes, this (re)implementsChris Lattner2006-02-271-3/+29
| | | | | | PowerPC/div-2.ll llvm-svn: 26392
* remove some completed notesChris Lattner2006-02-271-4/+0
| | | | llvm-svn: 26390
* Check RHS simplification before LHS simplification to avoid infinitely loopingChris Lattner2006-02-271-18/+17
| | | | | | on PowerPC/small-arguments.ll llvm-svn: 26389
* Just like we use the RHS of an AND to simplify the LHS, use the LHS toChris Lattner2006-02-271-0/+17
| | | | | | | | | | | | | | | | | | | | | simplify the RHS. This allows for the elimination of many thousands of ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2 into this: _test2: srwi r2, r3, 1 xori r3, r2, 40961 blr instead of this: _test2: rlwinm r2, r3, 31, 17, 31 xori r2, r2, 40961 rlwinm r3, r2, 0, 16, 31 blr llvm-svn: 26388
* Add a bunch of missed cases. Perhaps the most significant of which is thatChris Lattner2006-02-261-40/+206
| | | | | | assertzext produces zero bits. llvm-svn: 26386
* Fold (X|C1)^C2 -> X^(C1|C2) when possible. This implementsChris Lattner2006-02-261-0/+14
| | | | | | InstCombine/or.ll:test23. llvm-svn: 26385
* Reverting. Didn't realize some developers were embedding constants in theirJim Laskey2006-02-261-9/+1
| | | | | | target assembler code gen. llvm-svn: 26383
* ConstantPoolIndex is now the displacement portion of the address (ratherEvan Cheng2006-02-261-10/+4
| | | | | | than base). llvm-svn: 26382
* Print ConstantPoolSDNode offset field.Evan Cheng2006-02-261-0/+5
| | | | llvm-svn: 26381
* Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FPEvan Cheng2006-02-262-19/+31
| | | | | | and 2005-05-12-Int64ToFP. llvm-svn: 26380
* Format large struct constants for readability.Jim Laskey2006-02-251-4/+13
| | | | llvm-svn: 26379
* * Cleaned up addressing mode matching code.Evan Cheng2006-02-251-156/+127
| | | | | | | | * Cleaned up and tweaked LEA cost analysis code. Removed some hacks. * Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and they need to be matched before LEA. llvm-svn: 26376
* Updates.Evan Cheng2006-02-251-20/+3
| | | | llvm-svn: 26375
* * Allow mul, shl nodes to be codegen'd as LEA (if appropriate).Evan Cheng2006-02-251-1/+24
| | | | | | | | | * Add patterns to handle GlobalAddress, ConstantPool, etc. MOV32ri to materialize these nodes in registers. ADD32ri to handle %reg + GA, etc. MOV32mi to handle store GA, etc. to memory. llvm-svn: 26374
* ConstantPoolIndex is now the displacement field of addressing mode.Evan Cheng2006-02-251-3/+4
| | | | llvm-svn: 26373
* Added a common about the need for X86ISD::Wrapper.Evan Cheng2006-02-251-0/+7
| | | | llvm-svn: 26372
* Added an offset field to ConstantPoolSDNode.Evan Cheng2006-02-254-41/+31
| | | | llvm-svn: 26371
* Fix a bug that Evan exposed with some changes he's making, and that wasChris Lattner2006-02-251-9/+23
| | | | | | | | | exposed with a fastcc problem (breaking pcompress2 on x86 with -enable-x86-fastcc). When reloading a reused reg, make sure to invalidate the reloaded reg, and check to see if there are any other pending uses of the same register. llvm-svn: 26369
* Remove debugging printout :)Chris Lattner2006-02-251-5/+6
| | | | | | Add a minor compile time win, no codegen change. llvm-svn: 26368
* Refactor some code from being inline to being out in a new class with methods.Chris Lattner2006-02-251-42/+97
| | | | | | | | This gets rid of two gotos, which is always nice, and also adds some comments. No functionality change, this is just a refactor. llvm-svn: 26367
* Fix an obvious bug exposed when we are doingEvan Cheng2006-02-251-1/+2
| | | | | | | | ADD X, 4 ==> MOV32ri $X+4, ... llvm-svn: 26366
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