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* Reapply r198654 "indvars: sink truncates outside the loop."Andrew Trick2014-01-071-4/+23
| | | | | | | | | | | This doesn't seem to have actually broken anything. It was paranoia on my part. Trying again now that bots are more stable. This is a follow up of the r198338 commit that added truncates for lcssa phi nodes. Sinking the truncates below the phis cleans up the loop and simplifies subsequent analysis within the indvars pass. llvm-svn: 198678
* [AArch64 NEON] Fixed incorrect immediate used in BIC instruction.Kevin Qin2014-01-071-19/+93
| | | | llvm-svn: 198675
* ARM IAS: allow more depth in contextual diagnosticsSaleem Abdulrasool2014-01-071-20/+30
| | | | | | | Switch the context to be SmallVectors. This allows for saving additional context when providing previous emission sites. llvm-svn: 198665
* ARM IAS: refactor unwind contextSaleem Abdulrasool2014-01-071-56/+94
| | | | | | | | Move the unwinding context for the ARM IAS into a helper class. This is purely a structural refactoring. A follow up change allows for recording additional depth to improve diagnostics. llvm-svn: 198664
* ARM Streamer: print out tag namesSaleem Abdulrasool2014-01-071-5/+22
| | | | | | If using verbose asm, print out the friendly name of the tag if possible. llvm-svn: 198663
* ARM IAS: improve .eabi_attribute handlingSaleem Abdulrasool2014-01-076-19/+260
| | | | | | | | Parse tag names as well as expressions. The former is part of the specification, the latter is for improved compatibility with the GNU assembler. Fix attribute value handling to be comformant to the specification. llvm-svn: 198662
* MCParser: introduce Note and use it for ARM AsmParserSaleem Abdulrasool2014-01-072-6/+15
| | | | | | | | Introduce a new virtual method Note into the AsmParser. This completements the existing Warning and Error methods. Use the new method to clean up the output of the unwind routines in the ARM AsmParser. llvm-svn: 198661
* Fix comment of findGCD.Mingjie Xing2014-01-071-2/+2
| | | | llvm-svn: 198660
* Revert "indvars: sink truncates outside the loop."Andrew Trick2014-01-071-23/+4
| | | | | | | | This reverts commit r198654. One of the bots reported a SciMark failure. llvm-svn: 198659
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-072-49/+121
| | | | llvm-svn: 198658
* indvars: sink truncates outside the loop.Andrew Trick2014-01-071-4/+23
| | | | | | | | This is a follow up of the r198338 commit that added truncates for lcssa phi nodes. Sinking the truncates below the phis cleans up the loop and simplifies subsequent analysis within the indvars pass. llvm-svn: 198654
* 80 col. comment.Andrew Trick2014-01-071-2/+2
| | | | llvm-svn: 198653
* [Mips] TargetStreamer Support for .abicalls and .set pic0.Jack Carter2014-01-065-10/+77
| | | | | | | | | | This patch adds .abicalls and .set pic0 support which affects the ELF ABI and its flags. In addition the patch uses a common interface for both the MipsTargetSteamer and MipsObjectStreamer that both the integrated and standalone assemblers will use for the output for these directives. llvm-svn: 198646
* For the 'C' disassembler API, add a new ReferenceType for theKevin Enderby2014-01-062-0/+4
| | | | | | | | | | | | | | | | | | | SymbolLookUp() call back to return a demangled C++ name to be used as a comment. For example darwin's otool(1) program the uses the llvm disassembler now can produce disassembly like: callq __ZNK4llvm6Target20createMCDisassemblerERKNS_15MCSubtargetInfoE ## llvm::Target::createMCDisassembler(llvm::MCSubtargetInfo const&) const Also fix a bug in LLVMDisasmInstruction() that was not flushing the raw_svector_ostream for the disassembled instruction string before copying it to the output buffer that was causing truncation of the output. rdar://10173828 llvm-svn: 198637
* Improve documentation of the 'a' specifier and the '<abi>:<pref>' align pair.Rafael Espindola2014-01-061-0/+3
| | | | llvm-svn: 198636
* Reapply r198478 "Fix PR18361: Invalidate LoopDispositions after LoopSimplify ↵Andrew Trick2014-01-061-7/+14
| | | | | | | | | | hoists things." Now with a fix for PR18384: ValueHandleBase::ValueIsDeleted. We need to invalidate SCEV's loop info when we delete a block, even if no values are hoisted. llvm-svn: 198631
* Remove dead code.Rafael Espindola2014-01-061-8/+0
| | | | llvm-svn: 198624
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-0619-60/+67
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* XCore Target: correct callee save register spilling when callsUnwindInit is ↵Robert Lytton2014-01-062-2/+20
| | | | | | true. llvm-svn: 198616
* XCore target: Lower EH_RETURNRobert Lytton2014-01-064-0/+66
| | | | llvm-svn: 198615
* XCore target: Lower FRAME_TO_ARGS_OFFSETRobert Lytton2014-01-067-0/+102
| | | | | | | | | This requires a knowledge of the stack size which is not known until the frame is complete, hence the need for the XCoreFTAOElim pass which lowers the XCoreISD::FRAME_TO_ARGS_OFFSET instrution into its final form. llvm-svn: 198614
* XCore target: Lower RETURNADDRRobert Lytton2014-01-062-2/+26
| | | | | | Only handles a depth of zero (the same as FRAMEADDR) llvm-svn: 198613
* XCore target: Optimise entsp / retsp selectionRobert Lytton2014-01-061-1/+9
| | | | llvm-svn: 198612
* XCore target: Refactor LR handlingRobert Lytton2014-01-063-48/+72
| | | | | | | | | We also narrow the liveness of FP & LR during the prologue to reflect the actual usage of the registers. I have been unable to construct a test to prove the previous live range was too large. llvm-svn: 198611
* XCore target: Refactor the loading of constants into a registerRobert Lytton2014-01-063-32/+49
| | | | | | This common functionality will be used to lower FRAME_TO_ARGS_OFFSET. llvm-svn: 198610
* XCore target: fix handling of unsized global arrays in large code modelRobert Lytton2014-01-061-4/+13
| | | | llvm-svn: 198609
* ARM: keep special non-AEABIness of "-darwin-eabi" triples for nowTim Northover2014-01-061-2/+5
| | | | | | | | | | Longer term, we want to move users to "*-*-*-macho" for embedded work, but for now people are relying on the last thing we told them, which is unfortunately "*-*-darwin-eabi". rdar://problem/15703934 llvm-svn: 198602
* AVX-512: added intrinsic vcvtpd2ps (with rounding mode and without)Elena Demikhovsky2014-01-062-0/+9
| | | | llvm-svn: 198593
* [Sparc] Explicitly cast -1 to unsigned to fix buildbot errors.Venkatraman Govindaraju2014-01-061-8/+8
| | | | llvm-svn: 198592
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-0610-61/+371
| | | | llvm-svn: 198591
* MC: Fatally error if subtraction operand is badDavid Majnemer2014-01-062-5/+22
| | | | | | | | | Instead of crashing, raise an error when a subtraction expression involves an undefined symbol. This fixes PR18375. llvm-svn: 198590
* Remove SegOvrBits from X86 TSFlags since they weren't being used.Craig Topper2014-01-064-77/+46
| | | | llvm-svn: 198588
* Remove argument to fix build bot failure.Craig Topper2014-01-061-1/+1
| | | | llvm-svn: 198587
* Add OpSize16 bit, for instructions which need 0x66 prefix in 16-bit modeCraig Topper2014-01-063-31/+35
| | | | | | | | | | | | | | | | | The 0x66 prefix toggles between 16-bit and 32-bit addressing mode. So in 32-bit mode it is used to switch to 16-bit addressing mode for the following instruction, while in 16-bit mode it's the other way round — it's used to switch to 32-bit mode instead. Thus, emit the 0x66 prefix byte for OpSize only in 32-bit (and 64-bit) mode, and introduce a new OpSize16 bit which is used in 16-bit mode instead. This is just the basic infrastructure for that change; a subsequent patch will add the new OpSize16 bit to the 32-bit instructions that need it. Patch from David Woodhouse. llvm-svn: 198586
* Remove unnecessary #includes.Bill Wendling2014-01-068-8/+0
| | | | llvm-svn: 198585
* [x86] Add basic support for .code16Craig Topper2014-01-067-17/+79
| | | | | | | | | | | This is not really expected to work right yet. Mostly because we will still emit the OpSize (0x66) prefix in all the wrong places, along with a number of other corner cases. Those will all be fixed in the subsequent commits. Patch from David Woodhouse. llvm-svn: 198584
* [AArch64 NEON] Fix invalid constant used in vselect condition.Kevin Qin2014-01-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a wrong assumption that the vector element type and the type of each ConstantSDNode in the build_vector were the same. However, when promoting the integer operand of a legally typed build_vector, the operand type and the vector element type do not need to be the same (See method 'DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR' in LegalizeIntegerTypes.cpp). in AArch64 backend, the following dag sequence: C0: i1 = Constant<0> C1: i1 = Constant<-1> V: v8i1 = BUILD_VECTOR C1, C1, C0, C0, C0, C0, C0, C0 is type-legalized into: NewC0: i32 = Constant<0> NewC1: i32 = Constant<1> V: v8i8 = BUILD_VECTOR NewC1, NewC1, NewC0, NewC0, NewC0, NewC0, NewC0, NewC0 Forcing a getZeroExtend to VTBits to ensure that the new constant is correctly. llvm-svn: 198582
* [Sparc] Add ELF Object Writer for Sparc. Venkatraman Govindaraju2014-01-068-12/+287
| | | | llvm-svn: 198580
* Refactor function that checks that __builtin_returnaddress's argument is ↵Bill Wendling2014-01-069-32/+20
| | | | | | | | | constant. This moves the check up into the parent class so that all targets can use it without having to copy (and keep in sync) the same error message. llvm-svn: 198579
* ARM: move ARMUnwindOp.h into SupportSaleem Abdulrasool2014-01-064-154/+31
| | | | | | | | | Move the ARM EHABI unwind opcode definitions from the ARM MCTargetDesc into LLVM Support. This enables sharing of the definitions across the ARM target code as well as llvm-readobj. This will allow implementation of the unwind decoding in llvm-readobj. llvm-svn: 198576
* SPARC: Make helper function static.Benjamin Kramer2014-01-051-2/+2
| | | | llvm-svn: 198567
* Fix ModR/M byte output for 16-bit addressing modes (PR18220)Craig Topper2014-01-051-0/+60
| | | | | | | | | Add some tests to validate correct register selection, including a fix to an existing test which was requiring the *wrong* output. Patch from David Woodhouse. llvm-svn: 198566
* Remove opcode from MOV32r0 that I accidentally left when I converted it to ↵Craig Topper2014-01-051-2/+1
| | | | | | Pseudo. Remove FIXME as well. llvm-svn: 198564
* ARM: style changes to LDRD, STRD definitionSaleem Abdulrasool2014-01-051-11/+9
| | | | | | | | Fix indentation, name registers similar to ARM ARM. No functionality change! llvm-svn: 198563
* AVX-512: changed property name from "neverHasSideEffects=1" to ↵Elena Demikhovsky2014-01-052-24/+27
| | | | | | | | "hasSideEffects=0", added this property to VMOVSS/VMOVSD; Optimized a truncate pattern. llvm-svn: 198562
* AVX-512: Added more intrinsics for convert and min/max.Elena Demikhovsky2014-01-053-37/+46
| | | | | | Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all. llvm-svn: 198557
* [PM] Add a definition for the static PassID in the CallGraphAnalysis.Chandler Carruth2014-01-051-0/+6
| | | | | | | Missed this when adding the skeleton analysis. Caught by a build break in the next patch I'm working on when trying to use the analysis. llvm-svn: 198556
* Add the other form of movq xmm,xmm for the disassembler.Craig Topper2014-01-051-0/+9
| | | | llvm-svn: 198551
* Use patterns to remove some duplicate instructions.Craig Topper2014-01-051-8/+6
| | | | llvm-svn: 198550
* Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack.Craig Topper2014-01-051-2/+4
| | | | llvm-svn: 198547
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