summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* Disabled implicit-fallthrough warnings for ConvertUTF.cpp.Galina Kistanova2017-05-291-0/+31
| | | | | | | ConvertUTF.cpp has a little dependency on LLVM, and since the code extensively uses fall-through switches, I prefer disabling the warning for the whole file, rather than adding attributes for each case. llvm-svn: 304120
* DebugInfo: Include .dwo file name when hashing multiple CUs in a single fileDavid Blaikie2017-05-293-3/+13
| | | | | | | | | | | | | | | | | | | | This is really a workaround for ThinLTO in particular - since it can import partial CUs that may end up looking very similar/the same as the same partial import in another ThinLTO compile. An alternative fix would be to change the DICompileUnit metadata to include a "primary file" or the like - and when importing for ThinLTO set the primary file to the name of the DICompileUnit that is being imported into. This involves changing the schema and would reduce the excessive uniqueness in the hash that this change creates - allowing diagnosing of more duplicate CUs than will be caught with this change. But duplicate CUs can still be caught in non-ThinLTO builds & are mostly a nuisance rather than a particularly deliberate/effective tool for finding broken code. (arguably the hash could always include the dwo file and nothing in fission would break, I think..) llvm-svn: 304119
* Support: adjust the default obj format for wasmSaleem Abdulrasool2017-05-291-2/+4
| | | | | | | WebAssemly uses a custom object file format. For the wasm targets, default to the `Wasm` object file format. llvm-svn: 304117
* [AVR] Remove SREG from CPI's Uses; authored by Florian ZeitzDylan McKay2017-05-291-1/+0
| | | | | | | | | | | | | | Summary: CPI does not read the status register, but only writes it. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33223 llvm-svn: 304116
* [ItaniumDemangle] Fix a exponential string copying bugErik Pilkington2017-05-281-0/+3
| | | | | | This is a port of libcxxabi's r304113. llvm-svn: 304114
* Prune trailing whitespace. (To regenerate makefiles)NAKAMURA Takumi2017-05-281-2/+2
| | | | llvm-svn: 304112
* DebugInfo: Omit an empty CU when a subprogram was moved into its useDavid Blaikie2017-05-281-8/+12
| | | | | | | | When the only use of a CU is for a subprogram that's only emitted into the using CU (to avoid cross-CU references in DWO files), avoid creating that CU at all. llvm-svn: 304111
* [AArch64][Falkor] Combine sched details files into one. NFC.Geoff Berry2017-05-282-514/+503
| | | | llvm-svn: 304109
* [AArch64][Falkor] Fix some sched details.Geoff Berry2017-05-284-294/+461
| | | | | | | | | | | | | | | | | | | | - Remove all uses of base sched model entries and set them all to Unsupported so all the opcodes are described in AArch64SchedFalkorDetails.td. - Remove entries for unsupported half-float opcodes. - Remove entries for unsupported LSE extension opcodes. - Add entry for MOVbaseTLS (and set Sched in base td file entry to WriteSys) and a few other pseudo ops. - Fix a few FP load/store with reg offset entries to use the LSLfast predicates. - Add Q size BIF/BIT/BSL entries. - Fix swapped Q/D sized CLS/CLZ/CNT/RBIT entires. - Fix pre/post increment address register latency (this operand is always dest 0). - Fix swapped FCVTHD/FCVTHS/FCVTDH/FCVTDS entries. - Fix XYZ resource over usage on LD[1-4] opcodes. llvm-svn: 304108
* [InstrProf] Use more ArrayRef/StringRef.Benjamin Kramer2017-05-281-8/+8
| | | | | | No functional change intended. llvm-svn: 304089
* [X86] Adding new LLVM TableGen backend that generates the X86 backend memory ↵Ayman Musa2017-05-282-3398/+3
| | | | | | | | | | | folding tables. X86 backend holds huge tables in order to map between the register and memory forms of each instruction. This TableGen Backend automatically generated all these tables with the appropriate flags for each entry. Differential Revision: https://reviews.llvm.org/D32684 llvm-svn: 304088
* [X86] Adding FoldGenRegForm helper field (for memory folding tables tableGen ↵Ayman Musa2017-05-288-89/+175
| | | | | | | | | | | | | | | | | | | | | | backend) to X86Inst class and set its value for the relevant instructions. Some register-register instructions can be encoded in 2 different ways, this happens when 2 register operands can be folded (separately). For example if we look at the MOV8rr and MOV8rr_REV, both instructions perform exactly the same operation, but are encoded differently. Here is the relevant information about these instructions from Intel's 64-ia-32-architectures-software-developer-manual: Opcode Instruction Op/En 64-Bit Mode Compat/Leg Mode Description 8A /r MOV r8,r/m8 RM Valid Valid Move r/m8 to r8. 88 /r MOV r/m8,r8 MR Valid Valid Move r8 to r/m8. Here we can see that in order to enable the folding of the output and input registers, we had to define 2 "encodings", and as a result we got 2 move 8-bit register-register instructions. In the X86 backend, we define both of these instructions, usually one has a regular name (MOV8rr) while the other has "_REV" suffix (MOV8rr_REV), must be marked with isCodeGenOnly flag and is not emitted from CodeGen. Automatically generating the memory folding tables relies on matching encodings of instructions, but in these cases where we want to map both memory forms of the mov 8-bit (MOV8rm & MOV8mr) to MOV8rr (not to MOV8rr_REV) we have to somehow point from the MOV8rr_REV to the "regular" appropriate instruction which in this case is MOV8rr. This field enable this "pointing" mechanism - which is used in the TableGen backend for generating memory folding tables. Differential Revision: https://reviews.llvm.org/D32683 llvm-svn: 304087
* [X86] Fixing VPOPCNTDQ feature set lookup.Oren Ben Simhon2017-05-281-1/+1
| | | | llvm-svn: 304086
* Cloning: Fix debug info cloningGor Nishanov2017-05-273-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I believe https://reviews.llvm.org/rL302576 introduced two bugs: 1) it produces duplicate distinct variables for every: dbg.value describing the same variable. To fix the problme I switched form getDistinct() to get() in DebugLoc.cpp: auto reparentVar = [&](DILocalVariable *Var) { return DILocalVariable::getDistinct( 2) It passes NewFunction plain name as a linkagename parameter to Subprogram constructor. Breaks assert in: || DeclLinkageName.empty()) || LinkageName == DeclLinkageName) && "decl has a linkage name and it is different"' failed. #9 0x00007f5010261b75 llvm::DwarfUnit::applySubprogramDefinitionAttributes(llvm::DISubprogram const*, llvm::DIE&) /home/gor/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp:1173:3 # (Edit: reproducer added) Here how https://reviews.llvm.org/rL302576 broke coroutine debug info. Coroutine body of the original function is split into several parts by cloning and removing unneeded code. All parts describe the original function and variables present in the original function. For a simple case, prior to Split, original function has these two blocks: ``` PostSpill: ; preds = %AllocaSpillBB call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !14, metadata !15), !dbg !13 store i32 %x, i32* %x.addr, align 4 ... and sw.epilog: ; preds = %sw.bb %x.addr.reload.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 0, i32 4, !dbg !20 %4 = load i32, i32* %x.addr.reload.addr, align 4, !dbg !20 call void @llvm.dbg.value(metadata i32 %4, i64 0, metadata !14, metadata !15), !dbg !13 !14 = !DILocalVariable(name: "x", arg: 1, scope: !6, file: !7, line: 55, type: !11) ``` Note that in two blocks different expression represent the same original user variable X. Before rL302576, for every cloned function there was exactly one cloned DILocalVariable(name: "x" as in: ``` define i8* @f(i32 %x) #0 !dbg !6 { ... !6 = distinct !DISubprogram(name: "f", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, flags: DIFlagPrototyped, ... !14 = !DILocalVariable(name: "x", arg: 1, scope: !6, file: !7, line: 55, type: !11) define internal fastcc void @f.resume(%f.Frame* %FramePtr) #0 !dbg !25 { ... !25 = distinct !DISubprogram(name: "f", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !28 = !DILocalVariable(name: "x", arg: 1, scope: !25, file: !7, line: 55, type: !11) ``` After rL302576, for every cloned function there were as many DILocalVariable(name: "x" as there were "call void @llvm.dbg.value" for that variable. This was causing asserts in VerifyDebugInfo and AssemblyPrinter. Example: ``` !27 = distinct !DISubprogram(name: "f", linkageName: "f.resume", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, !29 = distinct !DILocalVariable(name: "x", arg: 1, scope: !27, file: !7, line: 55, type: !11) !39 = distinct !DILocalVariable(name: "x", arg: 1, scope: !27, file: !7, line: 55, type: !11) !41 = distinct !DILocalVariable(name: "x", arg: 1, scope: !27, file: !7, line: 55, type: !11) ``` Second problem: Prior to rL302576, all clones were described by DISubprogram referring to original function. ``` define i8* @f(i32 %x) #0 !dbg !6 { ... !6 = distinct !DISubprogram(name: "f", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, flags: DIFlagPrototyped, define internal fastcc void @f.resume(%f.Frame* %FramePtr) #0 !dbg !25 { ... !25 = distinct !DISubprogram(name: "f", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, flags: DIFlagPrototyped, ``` After rL302576, DISubprogram for clones is of two minds, plain name refers to the original name, linkageName refers to plain name of the clone. ``` !27 = distinct !DISubprogram(name: "f", linkageName: "f.resume", scope: !7, file: !7, line: 55, type: !8, isLocal: false, isDefinition: true, scopeLine: 55, ``` I think the assumption in AsmPrinter is that both name and linkageName should refer to the same entity. It asserts here when they are not: ``` || DeclLinkageName.empty()) || LinkageName == DeclLinkageName) && "decl has a linkage name and it is different"' failed. #9 0x00007f5010261b75 llvm::DwarfUnit::applySubprogramDefinitionAttributes(llvm::DISubprogram const*, llvm::DIE&) /home/gor/llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp:1173:3 ``` After this fix, behavior (with respect to coroutines) reverts to exactly as it was before and therefore making them debuggable again, or even more importantly, compilable, with "-g" Reviewers: dblaikie, echristo, aprantl Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33614 llvm-svn: 304079
* Recommit "[DWARF] - Make collectAddressRanges() return section index in ↵George Rimar2017-05-277-34/+62
| | | | | | | | | | | | | | | | | | | | | | addition to Low/High PC" With fix of uninitialized variable. Original commit message: This change is intended to use for LLD in D33183. Problem we have in LLD when building .gdb_index is that we need to know section which address range belongs to. Previously it was solved on LLD side by providing fake section addresses with use of llvm::LoadedObjectInfo interface. We assigned file offsets as addressed. Then after obtaining ranges lists, for each range we had to find section ID's. That not only was slow, but also complicated implementation and was the reason of incorrect behavior when sections share the same offsets, like D33176 shows. This patch makes DWARF parsers to return section index as well. That solves problem mentioned above. Differential revision: https://reviews.llvm.org/D33184 llvm-svn: 304078
* [TableGen] Prevent DagInit from leaking its Args and ArgNames when they ↵Craig Topper2017-05-271-11/+16
| | | | | | | | | | exceed the size of the SmallVector. DagInits are allocated in a BumpPtrAllocator so they are never destructed. This means the destructor for the SmallVector never runs. To fix this we now allocate the vectors in the BumpPtrAllocator too using TrailingObjects. llvm-svn: 304077
* [SCEV] Assume parameters coming from function calls contain IVsTobias Grosser2017-05-271-1/+4
| | | | | | | | | | | | | | | | | | | | The optimistic delinearization implemented in LLVM detects array sizes by looking for non-linear products between parameters and induction variables. In OpenCL code, such products often look like: A[get_global_id(0) * N + get_global_id(1)] Hence, the IV is hidden in the get_global_id() call and consequently delinearization would fail as no induction variable is available that helps us to identify N as array size parameter. We now use a very simple heuristic to change this. We assume that each parameter that comes directly from a function call is a hidden induction variable. As a result, we can delinearize the access above to: A[get_global_id(0)][get_global_id(1] llvm-svn: 304073
* [DAGCombiner] use narrow load to avoid vector extractSanjay Patel2017-05-271-0/+50
| | | | | | | | | | | | | | | | | | If we have (extract_subvector(load wide vector)) with no other users, that can just be (load narrow vector). This is intentionally conservative. Follow-ups may loosen the one-use constraint to account for the extract cost or just remove the one-use check. The memop chain updating is based on code that already exists multiple times in x86 lowering, so that should be pulled into a helper function as a follow-up. Background: this is a potential improvement noticed via regressions caused by making x86's peekThroughBitcasts() not loop on consecutive bitcasts (see comments in D33137). Differential Revision: https://reviews.llvm.org/D33578 llvm-svn: 304072
* [TableGen] Remove all the static vectors named TheActualPool.Craig Topper2017-05-271-12/+0
| | | | | | These used to hold std::unique_ptrs that managed the allocation for the various *Init object so that they would be deleted on exit. Everything is allocated in a BumpPtrAllocator name so there is no reason for these to still exist. llvm-svn: 304066
* [coroutines] Define getPassName() for coroutine passesGor Nishanov2017-05-274-0/+6
| | | | | | | | | | | | Reviewers: GorNishanov Reviewed By: GorNishanov Subscribers: EricWF, llvm-commits Differential Revision: https://reviews.llvm.org/D33622 llvm-svn: 304065
* [PartialInlining] Replace delete with unique_ptr in ↵Vitaly Buka2017-05-271-7/+3
| | | | | | | | | | | | | | computeCallsiteToProfCountMap Reviewers: davidxl Reviewed By: davidxl Subscribers: vsk, llvm-commits Differential Revision: https://reviews.llvm.org/D33220 llvm-svn: 304064
* AArch64/PEI: Do not add reserved regs to liveinsMatthias Braun2017-05-272-3/+7
| | | | | | | We do not track liveness for reserved registers. It is unnecessary to add them to block livein lists. llvm-svn: 304059
* [SCEVExpander] Try harder to avoid introducing inttoptrKeno Fischer2017-05-271-4/+16
| | | | | | | | | | | | | | | | Summary: This fixes introduction of an incorrect inttoptr/ptrtoint pair in the included test case which makes use of non-integral pointers. I suspect there are more cases like this left, but this takes care of the one I was seeing at the moment. Reviewers: sanjoy Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D33129 llvm-svn: 304058
* ScheduleDAGInstrs: Fix fixupKills()Matthias Braun2017-05-273-159/+51
| | | | | | | | | | | | Rewrite fixupKills() to use the LivePhysRegs class. Simplifies the code and fixes a bug where the CSR registers in return blocks where missed leading to invalid kill flags. Also remove the unnecessary rule that we wouldn't set kill flags on tied operands. No tests as I have an upcoming commit improving MachineVerifier checks to catch these cases in multiple existing lit tests. llvm-svn: 304055
* [Demangler] copy changes made in libcxxabi's r303718 to ItaniumDemangleErik Pilkington2017-05-271-21/+28
| | | | llvm-svn: 304053
* [AArch64][GlobalISel] Add the Localizer pass for the O0 pipelineQuentin Colombet2017-05-271-1/+9
| | | | | | | This should fix most of the issue we have right now with constants being spilled all over the place. llvm-svn: 304052
* [GlobalISel] Add a localizer pass for target to useQuentin Colombet2017-05-273-0/+127
| | | | | | | | | | | | | This reverts commit r299287 plus clean-ups. The localizer pass is a helper pass that could be run at O0 in the GISel pipeline to work around the deficiency of the fast register allocator. It basically shortens the live-ranges of the constants so that the allocator does not spill all over the place. Long term fix would be to make the greedy allocator fast. llvm-svn: 304051
* [GVN] Recommit the patch "Add phi-translate support in scalarpre".Wei Mi2017-05-271-21/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The recommit is to fix a bug about ExtractValue and InsertValue ops. For those ops, some varargs inside GVN::Expression are not value numbers but raw index numbers. It is wrong to do phi-translate for raw index numbers, and the fix is to stop doing that. Right now scalarpre doesn't have phi-translate support, so it will miss some simple pre opportunities. Like the following testcase, current scalarpre cannot recognize the last "a * b" is fully redundent because a and b used by the last "a * b" expr are both defined by phis. long a[100], b[100], g1, g2, g3; __attribute__((pure)) long goo(); void foo(long a, long b, long c, long d) { g1 = a * b; if (__builtin_expect(g2 > 3, 0)) { a = c; b = d; g2 = a * b; } g3 = a * b; // fully redundant. } The patch adds phi-translate support in scalarpre. This is only a temporary solution before the newpre based on newgvn is available. Differential Revision: https://reviews.llvm.org/D32252 llvm-svn: 304050
* BranchRelaxation: computeLiveIns() after creating new blockMatthias Braun2017-05-271-0/+4
| | | | | | | | One case in BranchRelaxation did not compute liveins after creating a new block. This is catched by existing tests with an upcoming commit that will improve MachineVerifier checking of livein lists. llvm-svn: 304049
* AArch64: Fix cmpxchg O0 expansionMatthias Braun2017-05-261-58/+61
| | | | | | | | | | | | | | - Rewrite livein calculation to use the computeLiveIns() helper function. This is slightly less efficient but easier to reason about and doesn't unnecessarily add pristine and reserved registers[1] - Zero the status register at the beginning of the loop to make sure it has a defined value. - Remove kill flags of values that need to stay alive throughout the loop. [1] An upcoming commit of mine will tighten the MachineVerifier to catch these. llvm-svn: 304048
* Bitcode: Remove some dead code. Spotted by Teresa.Peter Collingbourne2017-05-261-23/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D33609 llvm-svn: 304046
* [InstSimplify] Push commuted op checks for and/or of icmp further down to ↵Craig Topper2017-05-261-33/+47
| | | | | | | | | | | | avoid duplicate work Previously, we called simplifyPossiblyCastedAndOrOfICmps twice with the operands commuted, but the call to simplifyAndOrOfICmpsWithConstants further down already handles commuting and doesn't need to be called both ways. This patch pushes double calls further down to just the individual routines that need to be called twice. Differential Revision: https://reviews.llvm.org/D33603 llvm-svn: 304044
* [bpf] disallow global_addr+off foldingAlexei Starovoitov2017-05-262-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | Wrong assembly code is generated for a simple program with clang. If clang only produces IR and llc is used for IR lowering and optimization, correct assembly code is generated. The main reason is that clang feeds default Reloc::Static to llvm and llc feeds no RelocMode to llvm, where for llc case, BPF backend picks up Reloc::PIC_ mode. This leads different IR lowering behavior and clang permits global_addr+off folding while llc doesn't. This patch introduces isOffsetFoldingLegal function into BPF backend and the function always return false. This will make clang and llc behave the same for the lowering. Bug https://bugs.llvm.org//show_bug.cgi?id=33183 has more detailed explanation. Signed-off-by: Yonghong Song <yhs@fb.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 304043
* [Mips] Placate GCC's -Wmisleading-indentation. NFCI.Davide Italiano2017-05-261-17/+17
| | | | llvm-svn: 304041
* [lib/LTO] Don't reinvent the code for switching linkage.Davide Italiano2017-05-261-10/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D33582 llvm-svn: 304040
* LivePhysRegs: Rework constructor + documentation; NFCMatthias Braun2017-05-2610-22/+22
| | | | | | | - Take reference instead of pointer to a TRI that cannot be nullptr. - Improve documentation comments. llvm-svn: 304038
* LivePhysRegs: Add default for removeRegsInMask(Clobbers); NFCMatthias Braun2017-05-261-1/+1
| | | | llvm-svn: 304036
* MachineVerifier: Remove unused set; NFCMatthias Braun2017-05-261-5/+0
| | | | llvm-svn: 304035
* [Hexagon] Cleanup of unused function isCalleeSaveReg (NFC)Sumanth Gundapaneni2017-05-262-6/+0
| | | | llvm-svn: 304034
* Resubmit r303859 with test fixed.Konstantin Zhuravlyov2017-05-261-1/+3
| | | | | | | | | | [AMDGPU] add intrinsic for s_getpc Summary: The s_getpc instruction is exposed as intrinsic llvm.amdgcn.s.getpc. Patch by Tim Corringham llvm-svn: 304031
* Make helper functions static. NFC.Benjamin Kramer2017-05-268-12/+22
| | | | llvm-svn: 304029
* Fix the ManagedStatic list ordering when using ↵Frederich Munch2017-05-261-3/+8
| | | | | | | | | | | | | | | | | | | | DynamicLibrary::addPermanentLibrary. Summary: r295737 included a fix for leaking libraries loaded via. DynamicLibrary::addPermanentLibrary. This created a problem where static constructors in a library could insert llvm::ManagedStatic objects before DynamicLibrary would register it's own ManagedStatic, meaning a crash could occur at shutdown. r301562 exasperated this problem by cleaning up the DynamicLibrary ManagedStatic during llvm_shutdown. Reviewers: v.g.vassilev, lhames, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D33581 llvm-svn: 304027
* [InstSimplify] Move a variable declaration to make simplifyAndOfICmps look ↵Craig Topper2017-05-261-1/+1
| | | | | | more like simplifyOrOfICmps. NFC llvm-svn: 304023
* [InstSimplify] Use commutable matchers to shorten some codeCraig Topper2017-05-261-13/+5
| | | | | | | | This code was replicated two additional times to handle commuted cases, but I think a commutable matcher can take care of it. Differential Revision: https://reviews.llvm.org/D33585 llvm-svn: 304022
* [InstSimplify] Use m_APInt instead of m_ConstantInt in ((V + N) & C1) | (V & ↵Craig Topper2017-05-261-10/+10
| | | | | | | | | | C2) handling in order to support splat vectors. The tests here are have operands commuted to provide more coverage. I also commuted one of the instructions in the scalar tests so the 4 tests cover the 4 commuted variations Differential Revision: https://reviews.llvm.org/D33599 llvm-svn: 304021
* DebugInfo: Do not emit empty CUsDavid Blaikie2017-05-262-15/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consistent with GCC and addresses a shortcoming with ThinLTO where many imported CUs may end up being empty (because the functions imported from them either ended up not being used (and were then discarded, since they're imported as available_externally) or optimized away entirely). Test cases previously testing empty CUs (either intentionally, or because they didn't need anything more complicated) had a trivial 'int' or similar basic type added to their retained types list. This is a first order approximation - a deeper implementation could do things like: 1) Be more lazy about construction of the CU - for example if two CUs containing a single identical retained type are linked together, with this change one of the two CUs will be produced but empty (since a duplicate type won't be produced). 2) Go further and invert all the CU links the same way the subprogram link is inverted - keep named CU lists of retained types, macros, etc, and have those link back to the CU. Then if they're emitted, the CU is emitted, but never otherwise - this would allow the metadata itself to be dropped earlier too, though it seems unlikely that's an important optimization as there shouldn't be many CUs relative to the number of other entities. llvm-svn: 304020
* PMB: Run the whole-program-devirt pass during LTO at --lto-O0.Peter Collingbourne2017-05-261-0/+6
| | | | | | | | | | The whole-program-devirt pass needs to run at -O0 because only it knows about the llvm.type.checked.load intrinsic: it needs to both lower the intrinsic itself and handle it in the summary. Differential Revision: https://reviews.llvm.org/D33571 llvm-svn: 304019
* [InstCombine] Pass the DominatorTree, AssumptionCache, and context ↵Craig Topper2017-05-263-4/+7
| | | | | | | | | | instruction to a few calls to isKnownPositive, isKnownNegative, and isKnownNonZero Every other place in InstCombine that uses these methods in ValueTracking already pass this information. This makes the remaining sites consistent. Differential Revision: https://reviews.llvm.org/D33567 llvm-svn: 304018
* [AMDGPU][MC][GFX9] Corrected encoding of flat_scratch* for SDWA opcodesDmitry Preobrazhensky2017-05-261-1/+1
| | | | | | | | | | See bug 33171: https://bugs.llvm.org/show_bug.cgi?id=33171 Reviewers: Sam Kolton Differential Revision: https://reviews.llvm.org/D33553 llvm-svn: 304015
* Revert r304002 "[DWARF] - Make collectAddressRanges() return section index ↵George Rimar2017-05-267-61/+34
| | | | | | | | in addition to Low/High PC" Revert it again. Now another bot unhappy: http://lab.llvm.org:8011/builders/clang-s390x-linux/builds/8750 llvm-svn: 304011
OpenPOWER on IntegriCloud