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* [SystemZ] Add support for missing instructionsZhan Jun Liau2016-07-082-4/+93
| | | | | | | | | | | | | | | | | Summary: Add support to allow clang integrated assembler to recognize some missing instructions, for openssl. Instructions are: LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL. Reviewers: uweigand Subscribers: koriakin, llvm-commits Differential Revision: http://reviews.llvm.org/D22050 llvm-svn: 274869
* Move setName after accessing NameEric Liu2016-07-081-5/+2
| | | | llvm-svn: 274862
* Make a std::string copy of StringRef Name so that it remains valid when the ↵Eric Liu2016-07-081-1/+4
| | | | | | | | | | | | | | original Name is overridden. Summary: lib/IR/AutoUpgrade.cpp:348 and lib/IR/AutoUpgrade.cpp:350 upset sanitizer. Reviewers: bkramer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22140 llvm-svn: 274861
* [Sparc] Leon errata fix passes.Chris Dewhurst2016-07-088-173/+869
| | | | | | | | | | | | Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* InstCombine rule to fold truncs whose value is availableAnna Thomas2016-07-082-17/+50
| | | | | | | | | | | | | We can fold truncs whose operand feeds from a load, if the trunc value is available through a prior load/store. This change is from: http://reviews.llvm.org/D21246, which folded the trunc but missed the bitcast or ptrtoint/inttoptr required in the RAUW call, when the load type didnt match the prior load/store type. Differential Revision: http://reviews.llvm.org/D21791 llvm-svn: 274853
* [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)Valery Pykhtin2016-07-082-1/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D22049 llvm-svn: 274852
* Addressing post-commit comments regarding not expanding UDIV;Sjoerd Meijer2016-07-081-2/+2
| | | | | | we don't expand only when compiling for minimum code size. llvm-svn: 274847
* Code size optimisation: don't expand a div to a mul and and a shift sequence.Sjoerd Meijer2016-07-081-0/+5
| | | | | | | | | As a result, the urem instruction will not be expanded to a sequence of umull, lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod. Differential Revision: http://reviews.llvm.org/D22131 llvm-svn: 274843
* [AArch64] Macro fusion of simple ALU ops with branches for Broadcom's VulcanPankaj Gode2016-07-081-0/+1
| | | | | | | | | | Support for the macro fusion of simple ALU ops with branches for the Vulcan sub-target. Patch by Meador Inge <meadori@gmail.com> Differential Revision: http://reviews.llvm.org/D22042 llvm-svn: 274837
* [X86][SSE] Accept any shuffle mask that is all zeroesSimon Pilgrim2016-07-081-0/+7
| | | | | | Until we have a better way to extract constants through bitcasted build vectors (and how to handle undefs of partial lanes etc.) at least accept build vectors that are all zeroes. llvm-svn: 274833
* Bug 28444: Fix assertion when extract_vector_elt has mismatched typeMatt Arsenault2016-07-081-1/+1
| | | | | | | For some reason extract_vector_elt is sometimes allowed to have a different result type than the vector element type. llvm-svn: 274829
* [AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift ↵Craig Topper2016-07-083-15/+25
| | | | | | | | intrinsics. I'm not sure if clang ever used these builtin names or not. llvm-svn: 274827
* [PM] Port UnreachableBlockElim to the new Pass ManagerWei Mi2016-07-084-25/+41
| | | | | | Differential Revision: http://reviews.llvm.org/D22124 llvm-svn: 274824
* Add an assertion for the value enumerator (bitcode writer) NFCMehdi Amini2016-07-081-1/+6
| | | | | | | | I have an LTO snapshot (for which I don't have sources) that can't be read back by LLVM. It seems the writer emitted broken bitcode and this assertions aims at catching such cases. llvm-svn: 274819
* AMDGPU: Move si_mask_branch register operand to be a useMatt Arsenault2016-07-083-6/+8
| | | | llvm-svn: 274818
* AMDGPU: Cleanup. Use definesRegister instead of manual loopMatt Arsenault2016-07-081-6/+2
| | | | | | | Also this will be more precise since it will check exec_lo/exec_hi writes. llvm-svn: 274817
* ARM: support high registers in __builtin_longjmp on WoASaleem Abdulrasool2016-07-082-4/+34
| | | | | | | | | | Windows on ARM uses a pure thumb-2 environment. This means that it can select a high register when doing a __builtin_longjmp. We would use a tLDRi which would truncate the register to a low register. Use a t2LDRi12 to get the full register file access. Tweak the code to just load into PC, as that is an interworking branch on all supported cores anyways. llvm-svn: 274815
* [lanai] Use peephole optimizer to generate more conditional ALU operations.Jacques Pienaar2016-07-0715-364/+707
| | | | | | | | | | | | | | | | | Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 llvm-svn: 274807
* Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-074-1/+192
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
* [tsan] Try harder to not instrument gcov countersVedant Kumar2016-07-071-2/+2
| | | | | | | | GCOVProfiler::emitProfileArcs() can create many variables with names starting with "__llvm_gcov_ctr", so llvm appends a numeric suffix to most of them. Teach tsan about this. llvm-svn: 274801
* Add checks to the MachOObjectFile() constructor to make sure load commands sizesKevin Enderby2016-07-071-0/+19
| | | | | | are the correct multiple. llvm-svn: 274798
* [PM] Port InstSimplify to the new pass manager.Davide Italiano2016-07-073-44/+64
| | | | llvm-svn: 274796
* [DSE] Remove dead stores in end blocks containing fenceAnna Thomas2016-07-071-0/+8
| | | | | | | | | | We can remove dead stores in the presence of fence instructions. Fence does not change an otherwise thread local store to visible. reviewers: reames, dexonsmith, jfb Differential Revision: http://reviews.llvm.org/D22001 llvm-svn: 274795
* Add a missing semicolon.Rui Ueyama2016-07-071-1/+1
| | | | llvm-svn: 274794
* Clang-format LoadStoreVectorizerAlina Sbirlea2016-07-071-35/+33
| | | | | | | | | | Reviewers: llvm-commits, jlebar, arsenm Subscribers: mzolotukhin Differential Revision: http://reviews.llvm.org/D22107 llvm-svn: 274792
* [AArch64] Change the preferred alignment for char and short to word alignment.Chad Rosier2016-07-071-2/+2
| | | | | | | | | | The commit reinstates r273279, which was informally approved. Original Review: http://reviews.llvm.org/D21414 This reverts commit ca632c91aaa7cafc50942f890c49f727a046ace1. llvm-svn: 274790
* Include SelectionDAGISel in the opt-bisect processAndrew Kaylor2016-07-071-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D21143 llvm-svn: 274786
* ThinLTO: Do not take into account whether a definition has multiple copies ↵Peter Collingbourne2016-07-072-32/+6
| | | | | | | | | | | | | | | | | | | | | | when promoting. We currently do not touch a symbol's linkage in the case where a definition has a single copy. However, this code is effectively unnecessary: either the definition is not exported, in which case the internalize phase sets its linkage to internal, or it is exported, in which case we need to promote linkage to weak. Those two cases are already handled by existing code. I believe that the only real functional change here is in the case where we have a single definition which does not prevail (e.g. because the definition in a native object file prevails). In that case we now lower linkage to available_externally following the existing code path for that case. As a result we can remove the isExported function parameter from the thinLTOResolveWeakForLinkerInIndex function. Differential Revision: http://reviews.llvm.org/D21883 llvm-svn: 274784
* [LibFuzzer] Unbreak the build on macOS which was broken by r272858.Dan Liew2016-07-071-0/+6
| | | | | | | | | ``afl_driver.cpp`` currently relies on weak symbols which doesn't work properly under macOS. For now fix the build by providing a dummy implementation of ``LLVMFuzzerInitialize(...)``. This is just a temporary measure until we fix ``afl_driver.cpp`` for macOS. llvm-svn: 274778
* [LoopStrengthReduce] Fix -Wmisleading-indentation. Reported by GCC6.Davide Italiano2016-07-071-2/+2
| | | | llvm-svn: 274773
* Revert r274692 to check whether this is what breaks windows selfhost.Michael Kuperstein2016-07-074-189/+1
| | | | llvm-svn: 274771
* NVPTX: Remove the legacy ptx intrinsicsJustin Bogner2016-07-073-136/+86
| | | | | | | | | | | | - Rename the ptx.read.* intrinsics to nvvm.read.ptx.sreg.* - some but not all of these registers were already accessible via the nvvm name. - Rename ptx.bar.sync nvvm.bar.sync, to match nvvm.bar0. There's a fair amount of code motion here, but it's all very mechanical. llvm-svn: 274769
* Revert "[AArch64] Change the preferred alignment for char and short to word ↵Chad Rosier2016-07-071-2/+2
| | | | | | | | alignment" This reverts commit r273279 as the change was not properly approved. llvm-svn: 274768
* fix formatting; NFCSanjay Patel2016-07-071-16/+15
| | | | llvm-svn: 274765
* [SystemZ] Fix regression when handling conditional callsZhan Jun Liau2016-07-071-2/+2
| | | | | | | | | | | | | | | Summary: A regression showed up in node.js when handling conditional calls. Fix the regression by recognizing external symbols as a possible operand type in CallJG. Reviewers: koriakin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22054 llvm-svn: 274761
* save type in local var; NFCISanjay Patel2016-07-071-10/+11
| | | | llvm-svn: 274760
* Addressing post-commit comments for not rewriting fputs:Sjoerd Meijer2016-07-071-2/+5
| | | | | | moved the optimise for size check inside function optimizeFPuts. llvm-svn: 274758
* [AMDGPU] fix ds_write_src2 encoding (bz26027)Valery Pykhtin2016-07-072-2/+16
| | | | | | Differential revision: http://reviews.llvm.org/D22041 llvm-svn: 274756
* Don't crash trying to relax 32 loads on COFF.Rafael Espindola2016-07-071-0/+1
| | | | | | Fixes pr28452. llvm-svn: 274754
* Code size optimisation: don't rewrite fputs to fwrite when optimising for sizeSjoerd Meijer2016-07-071-0/+2
| | | | | | because fwrite requires more arguments and thus extra MOVs are required. llvm-svn: 274753
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 1 flagDiana Picus2016-07-074-12/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes a command line flag that isn't used in any of the tests: check-vmlx-hazards. It can be replaced easily with the mattr mechanism, since this is now a subtarget feature. There is still some work left regarding FeatureExpandMLx. In the past MLx expansion was enabled for subtargets with hasVFP2(), until r129775 [1] switched from that to isCortexA9, without too much justification. In spite of that, the code performing MLx expansion still contains calls to isSwift/isLikeA9, although the results of those are pretty clear given that we're only enabling it for the A9. We should try to enable it for all targets that have FeatureHasVMLxHazards, as it seems to be closely related to that behaviour, and if that is possible try to clean up the MLx expansion pass from all calls to isWhatever. This will require some performance testing, so it will be done in another patch. [1] http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20110418/119725.html Differential Revision: http://reviews.llvm.org/D21798 llvm-svn: 274742
* [LCG] Hoist the definitions of the stream operator friends to be inlineChandler Carruth2016-07-071-42/+0
| | | | | | | | | | | friend definitions. Based on the experiments Sean Silva and Reid did, this seems the safest course of action and also will work around a questionable warning provided by GCC6 on the old form of the code. Thanks for Davide pointing out the issue and other suggesting ways to fix. llvm-svn: 274740
* [LoopAccessAnalysis] Fix an integer overflowDavid Majnemer2016-07-071-22/+22
| | | | | | | | | We were inappropriately using 32-bit types to account for quantities that can be far larger. Fixed in PR28443. llvm-svn: 274737
* [AVX512] Zero extend the result of vpcmpeq/vpcmpgt and similar intrinsics in ↵Craig Topper2016-07-071-2/+3
| | | | | | the autoupgrade code. This currently results in worse codegen but is needed for correctness. llvm-svn: 274736
* Fixed a bug in vectorizing GEP before gather/scatter intrinsic.Elena Demikhovsky2016-07-071-8/+11
| | | | | | | | | | Vectorizing GEP was incorrect and broke SSA in some cases. The patch fixes PR27997 https://llvm.org/bugs/show_bug.cgi?id=27997. Differential revision: http://reviews.llvm.org/D22035 llvm-svn: 274735
* [CodeView] Implement support for thread-local variablesDavid Majnemer2016-07-071-4/+15
| | | | llvm-svn: 274734
* [esan:cfrag] Add option -esan-aux-field-infoQin Zhao2016-07-071-44/+66
| | | | | | | | | | | | | | | | | | | Summary: Adds option -esan-aux-field-info to control generating binary with auxiliary struct field information. Extracts code for creating auxiliary information from createCacheFragInfoGV into createCacheFragAuxGV. Adds test struct_field_small.ll for -esan-aux-field-info test. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D22019 llvm-svn: 274726
* ThinLTO: Remove check for multiple modules before applying weak resolutions.Peter Collingbourne2016-07-071-4/+0
| | | | | | | | | | This check is not only unnecessary, it can produce the wrong result. If we are linking a single module and it has an exported linkonce symbol, we need to promote to weak in order to avoid PR19901-style problems. Differential Revision: http://reviews.llvm.org/D21917 llvm-svn: 274722
* Use the class version of getPointerTy rather than getting back toEric Christopher2016-07-071-23/+22
| | | | | | ourselves via a call through the DAG. llvm-svn: 274721
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