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* Change to depth-first traversal.Evan Cheng2007-05-181-11/+22
| | | | llvm-svn: 37236
* Document an inefficiency in tail merging.Dale Johannesen2007-05-181-0/+19
| | | | llvm-svn: 37235
* Use MVT::FIRST_VECTOR_VALUETYPE and MVT::LAST_VECTOR_VALUETYPE.Dan Gohman2007-05-181-2/+2
| | | | llvm-svn: 37234
* Qualify calls to getTypeForValueType with MVT:: too.Dan Gohman2007-05-181-3/+3
| | | | llvm-svn: 37233
* Some restructuring in preparation for most aggressive if-conversion.Evan Cheng2007-05-181-40/+71
| | | | llvm-svn: 37231
* Qualify several calls to functions in the MVT namespace, for consistency.Dan Gohman2007-05-184-23/+25
| | | | llvm-svn: 37230
* Watch out for blocks that end with a return.Evan Cheng2007-05-181-2/+2
| | | | llvm-svn: 37227
* Fix PR1434 and test/Linker/link-archive.ll, this is a regression from 1.9.Chris Lattner2007-05-182-54/+91
| | | | llvm-svn: 37204
* If true / false blocks fallthrough before ifcvt, add unconditional branches ↵Evan Cheng2007-05-181-4/+19
| | | | | | to ifcvt'd block. llvm-svn: 37200
* Mark calls non-predicable for now. Need to ensure it's the last instruction ↵Evan Cheng2007-05-181-8/+8
| | | | | | in the if-converted block or make sure it preserve condition code. llvm-svn: 37199
* Remove some unneeded branches. (spotted by Evan, thanks)Dale Johannesen2007-05-181-0/+1
| | | | llvm-svn: 37198
* Silence some compilation warnings.Evan Cheng2007-05-181-2/+2
| | | | llvm-svn: 37197
* Make use of target specific block size limits; bug fixes.Evan Cheng2007-05-181-64/+149
| | | | llvm-svn: 37195
* Set ARM if-conversion block size threshold to 10 instructions for now.Evan Cheng2007-05-181-2/+2
| | | | llvm-svn: 37194
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-186-30/+37
| | | | | | / inserted. llvm-svn: 37193
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-186-28/+35
| | | | | | / inserted. llvm-svn: 37192
* Move isSuccessor() offline, change it to use std::find.Evan Cheng2007-05-171-0/+6
| | | | llvm-svn: 37190
* Fix PR1431Devang Patel2007-05-171-1/+1
| | | | | | Test case at Transformations/SCCP/2007-05-16-InvokeCrash.ll llvm-svn: 37185
* More effective breakdown of memcpy into repeated load/store. These are nowDale Johannesen2007-05-172-1/+77
| | | | | | | | in the order lod;lod;lod;sto;sto;sto which means the load-store optimizer has a better chance of producing ldm/stm. Ideally you would get cooperation from the RA as well but this is not there yet. llvm-svn: 37179
* Get rid of leading zeros in the output of toString.Reid Spencer2007-05-171-8/+27
| | | | llvm-svn: 37175
* Fix a bogus check that prevented folding VECTOR_SHUFFLE to UNDEF; add an ↵Evan Cheng2007-05-171-24/+61
| | | | | | optimization to fold VECTOR_SHUFFLE to a zero vector. llvm-svn: 37173
* Added missing patterns for UNPCKH* and PUNPCKH*.Evan Cheng2007-05-171-0/+20
| | | | llvm-svn: 37172
* disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits forChris Lattner2007-05-171-0/+13
| | | | | | | i128 integers. The 64-bit masks are not wide enough to represent the results. These should be converted to APInt someday. llvm-svn: 37169
* add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub ↵Chris Lattner2007-05-171-0/+42
| | | | | | on 32-bit (or less) targets llvm-svn: 37168
* This is the correct fix for PR1427. This fixes mmx-shuffle.ll and doesn'tChris Lattner2007-05-171-2/+5
| | | | | | cause other regressions. llvm-svn: 37160
* Revert patch for PR1427. It breaks almost all vector tests.Anton Korobeynikov2007-05-171-10/+1
| | | | llvm-svn: 37159
* add support for 128-bit add/sub on ppc64Chris Lattner2007-05-171-0/+34
| | | | llvm-svn: 37158
* Print integer values as both decimal and hexadecimal for convenienceReid Spencer2007-05-171-1/+1
| | | | | | of verifying result values when debugging. llvm-svn: 37156
* add support for 128-bit integer add/subChris Lattner2007-05-171-0/+20
| | | | llvm-svn: 37154
* For lshr by 0 bits, just return *this as a short cut. This also preventsReid Spencer2007-05-171-0/+6
| | | | | | undefined behavior when the width > 64 bits. llvm-svn: 37153
* Fix PR1427 and test/CodeGen/X86/mmx-shuffle.llChris Lattner2007-05-171-1/+10
| | | | llvm-svn: 37141
* Remove. Not needed.Evan Cheng2007-05-171-4/+0
| | | | llvm-svn: 37139
* Default implementation of TargetInstrInfo::getBlockSize().Evan Cheng2007-05-161-0/+4
| | | | llvm-svn: 37138
* Add target hook to specify block size limit for if-conversion.Evan Cheng2007-05-161-0/+1
| | | | llvm-svn: 37134
* Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.Dale Johannesen2007-05-161-1/+3
| | | | llvm-svn: 37130
* isBlockPredicable() always ignore terminal instructions; add comments.Evan Cheng2007-05-161-13/+23
| | | | llvm-svn: 37126
* ARM::tB is also predicable.Evan Cheng2007-05-161-2/+5
| | | | llvm-svn: 37125
* PredicateInstruction returns true if the operation was successful.Evan Cheng2007-05-163-18/+27
| | | | llvm-svn: 37124
* Add default implementation of PredicateInstruction().Evan Cheng2007-05-161-0/+20
| | | | llvm-svn: 37123
* Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr.Evan Cheng2007-05-162-14/+18
| | | | llvm-svn: 37121
* Move if-conversion after all passes that may use register scavenger.Evan Cheng2007-05-162-9/+3
| | | | llvm-svn: 37120
* Removed isPredicable().Evan Cheng2007-05-162-10/+0
| | | | llvm-svn: 37119
* Make ARM::B isPredicable; Make Bcc and MOVCC condition option a normal ↵Evan Cheng2007-05-161-5/+6
| | | | | | operand so they are not predicable. llvm-svn: 37118
* Added isPredicable bit to class Instruction.Evan Cheng2007-05-161-0/+1
| | | | llvm-svn: 37117
* Fix a bug in the "fromString" method where radix 2,8 and 16 values wereReid Spencer2007-05-161-8/+13
| | | | | | | | not being generated correctly because the shl operator does not mutate its object but returns a new value. Also, make the distinction between radix 16 and the others more clear. llvm-svn: 37111
* Avoid a "loss of precision" error in gcc 4.1.3.Reid Spencer2007-05-161-1/+1
| | | | llvm-svn: 37105
* Output exception call-sites in address order, as required by the unwindingDuncan Sands2007-05-161-10/+54
| | | | | | runtime. llvm-svn: 37104
* Conditional branch is not a barrier.Evan Cheng2007-05-161-4/+6
| | | | llvm-svn: 37103
* Use a ptr set instead of a linear search to unique TokenFactor operands.Chris Lattner2007-05-161-10/+13
| | | | | | This fixes PR1423 llvm-svn: 37102
* implement the missing maskmovq mmx intrinsic that akor hit.Chris Lattner2007-05-161-1/+3
| | | | llvm-svn: 37100
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