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* [Hexagon] Silence unused variable warning in Release buildsBenjamin Kramer2018-03-231-2/+2
| | | | llvm-svn: 328356
* [Hexagon] Fold offset in base+immediate loads/storesKrzysztof Parzyszek2018-03-231-9/+183
| | | | | | | | Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz. Patch by Jyotsna Verma. llvm-svn: 328355
* [X86] Add itinerary to RCPSS*_Int and similar instructions.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328353
* [X86] Add itineraries to ADD.*_DB instructions to match their normal ↵Craig Topper2018-03-231-11/+20
| | | | | | counterparts. llvm-svn: 328352
* [AMDGPU] Remove use of OpenCL triple environment and replace with function ↵Tony Tye2018-03-232-10/+4
| | | | | | | | | | | attribute for AMDGPU - Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target. - Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS. Differential Revision: https://reviews.llvm.org/D43736 llvm-svn: 328349
* [PDB] Make our PDBs look more like MS PDBs.Zachary Turner2018-03-237-47/+146
| | | | | | | | | | | | | | | | | | When investigating bugs in PDB generation, the first step is often to do the same link with link.exe and then compare PDBs. But comparing PDBs is hard because two completely different byte sequences can both be correct, so it hampers the investigation when you also have to spend time figuring out not just which bytes are different, but also if the difference is meaningful. This patch fixes a couple of cases related to string table emission, hash table emission, and the order in which we emit strings that makes more of our bytes the same as the bytes generated by MS PDBs. Differential Revision: https://reviews.llvm.org/D44810 llvm-svn: 328348
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-231-2/+10
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [Hexagon] Avoid early if-conversion for one sided branchesKrzysztof Parzyszek2018-03-231-12/+19
| | | | | | Patch by Anand Kodnani. llvm-svn: 328344
* [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function ↵Simon Pilgrim2018-03-231-6/+6
| | | | | | unit llvm-svn: 328343
* [HWASan] Port HWASan to Linux x86-64 (LLVM)Alex Shlyapnikov2018-03-231-13/+58
| | | | | | | | | | | | | | | | | | | | | Summary: Porting HWASan to Linux x86-64, first of the three patches, LLVM part. The approach is similar to ARM case, trap signal is used to communicate memory tag check failure. int3 instruction is used to generate a signal, access parameters are stored in nop [eax + offset] instruction immediately following the int3 one. One notable difference is that x86-64 has to untag the pointer before use due to the lack of feature comparable to ARM's TBI (Top Byte Ignore). Reviewers: eugenis Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D44699 llvm-svn: 328342
* [ARM] Fix "Constant pool entry out of range!" in Thumb1 modeAna Pazos2018-03-231-0/+1
| | | | | | | | | | | | | | | | | | | This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode. In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode, adjustBBOffsetsAfter() is not calculating postOffset correctly by properly accounting for the padding that is required for the constant pool that immediately follows the jump table branch instruction. Reviewers: t.p.northover, eli.friedman Reviewed By: t.p.northover Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D44709 llvm-svn: 328341
* [Hexagon] Two fixes in early if-conversionKrzysztof Parzyszek2018-03-231-9/+12
| | | | | | | | | - Fix checking for vector predicate registers. - Avoid speculating llvm.lifetime.end intrinsic. Patch by Harsha Jagasia and Brendon Cahoon. llvm-svn: 328339
* [X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unitSimon Pilgrim2018-03-231-2/+4
| | | | | | Add missing non-VEX and (V)PMOVMSKB instructions to the pattern llvm-svn: 328338
* Fix a block copying problem in LICMAndrew Kaylor2018-03-231-2/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D44817 llvm-svn: 328336
* [ADT] Simplify getMemory. NFCFangrui Song2018-03-231-5/+2
| | | | llvm-svn: 328334
* [Hexagon] Copy subregisters in HexagonStoreWidenKrzysztof Parzyszek2018-03-231-8/+10
| | | | | | | | | When converting an instruction to the wider version, copy any subregisters if the original operand has a subregister. Patch by Brendon Cahoon. llvm-svn: 328333
* [X86][Btver2] Vector permutes use a JFPU01 scheduler pipe and JFPX/JVALU ↵Simon Pilgrim2018-03-231-18/+18
| | | | | | function unit llvm-svn: 328331
* [X86][Btver2] Vector store instructions use a JFPU1 scheduler pipe and ↵Simon Pilgrim2018-03-231-2/+2
| | | | | | JSAGU/JSTC function units llvm-svn: 328328
* Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-236-45/+139
| | | | | | | | | | | | | | | | This patch adds functions to allow MachineLICM to hoist invariant stores. Currently, MachineLICM does not hoist any store instructions, however when storing the same value to a constant spot on the stack, the store instruction should be considered invariant and be hoisted. The function isInvariantStore iterates each operand of the store instruction and checks that each register operand satisfies isCallerPreservedPhysReg. The store may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore. This patch also adds the PowerPC changes needed to consider the stack register as caller preserved. Differential Revision: https://reviews.llvm.org/D40196 llvm-svn: 328326
* [X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function unitsSimon Pilgrim2018-03-231-12/+12
| | | | llvm-svn: 328324
* [InstCombine] reduce code duplication; NFCSanjay Patel2018-03-231-56/+49
| | | | llvm-svn: 328323
* [InstCombine] improve variable name; NFCSanjay Patel2018-03-231-12/+10
| | | | llvm-svn: 328322
* [AArch64] Don't reduce the width of loads if it prevents combining a shiftJohn Brawn2018-03-232-0/+30
| | | | | | | | | | | | | | | Loads and stores can only shift the offset register by the size of the value being loaded, but currently the DAGCombiner will reduce the width of the load if it's followed by a trunc making it impossible to later combine the shift. Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and make it prevent the width reduction if this is what would happen, though do allow it if reducing the load width will let us eliminate a later sign or zero extend. Differential Revision: https://reviews.llvm.org/D44794 llvm-svn: 328321
* [X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructionsSimon Pilgrim2018-03-231-3/+3
| | | | | | This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops. llvm-svn: 328320
* [X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instructions to ↵Simon Pilgrim2018-03-231-5/+5
| | | | | | | | correctly use JFPU1 scheduler pipe followed by JLAGU/JSAGU/JFPA/JVALU function units Fixes throughput to match Agner/Fam16h-SoG as well. llvm-svn: 328318
* [SLP] Stop counting cost of gather sequences with multiple usesMatthew Simpson2018-03-231-1/+22
| | | | | | | | | | | | | | | When building the SLP tree, we look for reuse among the vectorized tree entries. However, each gather sequence is represented by a unique tree entry, even though the sequence may be identical to another one. This means, for example, that a gather sequence with two uses will be counted twice when computing the cost of the tree. We should only count the cost of the definition of a gather sequence rather than its uses. During code generation, the redundant gather sequences are emitted, but we optimize them away with CSE. So it looks like this problem just affects the cost model. Differential Revision: https://reviews.llvm.org/D44742 llvm-svn: 328316
* [DEBUGINFO] Add flag for DWARF2 to use sections as references.Alexey Bataev2018-03-233-6/+41
| | | | | | | | | | | | | | | Summary: Some targets does not support labels inside debug sections, but support references in form `section+offset`. Patch adds initial support for this. Reviewers: echristo, probinson, jlebar Subscribers: llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D43943 llvm-svn: 328314
* [ARM] Support float literals under XOChristof Douma2018-03-233-12/+30
| | | | | | | | | | | | | When targeting execute-only and fp-armv8, float constants in a compare resulted in instruction selection failures. This is now fixed by using vmov.f32 where possible, otherwise the floating point constant is lowered into a integer constant that is moved into a floating point register. This patch also restores using fpcmp with immediate 0 under fp-armv8. Change-Id: Ie87229706f4ed879a0c0cf66631b6047ed6c6443 llvm-svn: 328313
* Revert r328307: [IPSCCP] Use constant range information for comparisons of ↵Florian Hahn2018-03-231-17/+50
| | | | | | | | parameters. Reverted for now, due to it causing verifier failures. llvm-svn: 328312
* [X86][Znver1] Fix instregex entries that don't match any instructions (D44687)Simon Pilgrim2018-03-231-4/+3
| | | | | | Reviewed by @GGanesh and @craig.topper llvm-svn: 328309
* [X86][SandyBridge] Fix missing comma that was causing string concatenation ↵Simon Pilgrim2018-03-231-1/+1
| | | | | | | | of 2 instregex entries Found while updating D44687 llvm-svn: 328308
* [IPSCCP] Use constant range information for comparisons of parameters.Florian Hahn2018-03-231-50/+17
| | | | | | | | | | | | | | | | | | For comparisons with parameters, we can use the ParamState lattice elements which also provide constant range information. This improves the code for PR33253 further and gets us closer to use ValueLatticeElement for all values. Also, as we are using the range information in the solver directly, we do not need tryToReplaceWithConstantRange afterwards anymore. Reviewers: dberlin, mssimpso, davide, efriedma Reviewed By: mssimpso Differential Revision: https://reviews.llvm.org/D43762 llvm-svn: 328307
* [X86][Btver2] Vector move/load/store instructions use a JFPU01 scheduler ↵Simon Pilgrim2018-03-231-6/+6
| | | | | | pipe and JFPX/JVALU function unit as well as the AGUs llvm-svn: 328304
* [AArch64] Clean-up a few over-eager regexps in models.Florian Hahn2018-03-232-26/+26
| | | | | | | | | Patch by Simon Pilgrim <llvm-dev@redking.me.uk> That is a slightly modified version of the AArch64 changes from Simon's D44687 . llvm-svn: 328303
* [LoopUnroll] Simplify induction variables after peeling too.Florian Hahn2018-03-231-2/+3
| | | | | | | | | | | | | Loop peeling also has an impact on the induction variables, so we should benefit from induction variable simplification after peeling too. Reviewers: sanjoy, bogner, mzolotukhin, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D43878 llvm-svn: 328301
* [ARM] Error out on .arm assembler directives on windowsMartin Storsjo2018-03-231-0/+7
| | | | | | | | Windows on arm is thumb only. Differential Revision: https://reviews.llvm.org/D43005 llvm-svn: 328298
* Revert "[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))"Martin Storsjo2018-03-231-80/+0
| | | | | | | This reverts commit r328252. This change broke building a number of projects when targeting ARM and AArch64, see PR36873. llvm-svn: 328297
* [X86] Give VPCMPEQQ the same itinerary as its SSE counterpart.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328296
* [X86] Correct the latencies of SNB integer vector multiplies based on ↵Craig Topper2018-03-231-9/+25
| | | | | | Agner's data. Add missing MMX multiplies. llvm-svn: 328295
* [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to the SSE equivalent. ↵Craig Topper2018-03-231-28/+23
| | | | | | Change pblendvb/blendvps/blendvpd to use WriteFVarBlend llvm-svn: 328294
* [X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to match the SSE version.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328293
* [X86] Give VLDDQUrm and LDDQUrm the same itinerary.Craig Topper2018-03-231-3/+4
| | | | llvm-svn: 328292
* [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model.Craig Topper2018-03-231-3/+2
| | | | | | The VMOVMSKBrr was in a separate InstRW with a lower latency, but I assume they should be the same and the higher latency matches Agners table so I'm going with that. llvm-svn: 328291
* [X86] Add VEXTRB/W/D/Q to Zen scheduler model.Craig Topper2018-03-231-2/+2
| | | | | | The SSE versions were present, but not the VEX version. llvm-svn: 328290
* [X86] Fix the itinerary for vextractps to match extractps.Craig Topper2018-03-231-2/+2
| | | | llvm-svn: 328289
* [DAG] Fix node id invalidation in Instruction Selection.Nirav Dave2018-03-231-3/+3
| | | | | | Invalidation should be bit negation. Add missing negation. llvm-svn: 328287
* State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'.Michael Zolotukhin2018-03-221-0/+1
| | | | | | That removes some redundant recomputations from the passes pipeline. llvm-svn: 328272
* Move SampleProfile.h into IPO along with the rest of the IPO pass headersDavid Blaikie2018-03-222-2/+2
| | | | llvm-svn: 328262
* [X86] Correct the VROUND regular expressions in Znver1 scheduler model to ↵Craig Topper2018-03-221-2/+2
| | | | | | account for r328254 llvm-svn: 328260
* Finish moving the IPSCCP pass from Scalar to IPO - moving the registrationDavid Blaikie2018-03-222-1/+1
| | | | llvm-svn: 328259
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