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* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-1815-48/+48
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* [Verifier] Assert gc_relocate always return a pointer type Chen Li2015-05-181-2/+12
| | | | | | | | | | | | | | Summary: Add an assertion in verifier.cpp to make sure gc_relocate relocate a gc pointer, and its return type has the same address space with the relocated pointer. Reviewers: reames, AndyAyers, sanjoy, pgavlin Reviewed By: pgavlin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9695 llvm-svn: 237605
* [PlaceSafepoints] Assertion on that gc_result can not have preceding phis ↵Chen Li2015-05-181-2/+2
| | | | | | | | | | | | | | | | should only apply to invoke statepoint Summary: When PlaceSafepoints pass replaces old return result with gc_result from statepoint, it asserts that gc_result can not have preceding phis in its parent block. This is only true on invoke statepoint, which terminates the block and puts its result at the beginning of the normal successor block. Call statepoint does not terminate the block and thus its result is in the same block with it. There should be no restriction on whether there are phis or not. Reviewers: reames, igor-laevsky Reviewed By: igor-laevsky Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9803 llvm-svn: 237597
* MC: clang-format MCContext. NFC.Jim Grosbach2015-05-181-8/+9
| | | | llvm-svn: 237595
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-1874-279/+279
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* Exploit dereferenceable_or_null attribute in LICM passSanjoy Das2015-05-182-30/+114
| | | | | | | | | | | | | | | | | | | | Summary: Allow hoisting of loads from values marked with dereferenceable_or_null attribute. For values marked with the attribute perform context-sensitive analysis to determine whether it's known-non-null or not. Patch by Artur Pilipenko! Reviewers: hfinkel, sanjoy, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9253 llvm-svn: 237593
* ARM: allow jump tables to be placed as constant islands.Tim Northover2015-05-187-170/+312
| | | | | | | | | | | | | | | | | Previously, they were forced to immediately follow the actual branch instruction. This was usually OK (the LEAs actually accessing them got emitted nearby, and weren't usually separated much afterwards). Unfortunately, a sufficiently nasty phi elimination dumps many instructions right before the basic block terminator, and this can increase the range too much. This patch frees them up to be placed as usual by the constant islands pass, and consequently has to slightly modify the form of TBB/TBH tables to refer to a PC-relative label at the final jump. The other jump table formats were already position-independent. rdar://20813304 llvm-svn: 237590
* [ScalarEvolution] refactor: extract interface getGEPExprJingyue Wu2015-05-182-56/+73
| | | | | | | | | | | | | | | | | | Summary: This allows other passes (such as SLSR) to compute the SCEV expression for an imaginary GEP. Test Plan: no regression Reviewers: atrick, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9786 llvm-svn: 237589
* indvars cruft: don't replace phi nodes for no reason.Andrew Trick2015-05-181-10/+0
| | | | | | | | | Don't replace a phi with an identical phi. This was done long ago to "preserve" IVUsers analysis. The code has already called SE->forgetValue(PN) so I see no purpose in creating a new value for the phi. llvm-svn: 237587
* SimplifyIV comments and dead argument cleanup.Andrew Trick2015-05-182-7/+5
| | | | | | Remove crufty comments. IVUsers hasn't been used here for a long time. llvm-svn: 237586
* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-183-2/+74
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Preserve the order of READ_REGISTER and WRITE_REGISTERHal Finkel2015-05-182-5/+9
| | | | | | | | | | | | | At the present time, we don't have a way to represent general dependency relationships, so everything is represented using memory dependency. In order to preserve the data dependency of a READ_REGISTER on WRITE_REGISTER, we need to model WRITE_REGISTER as writing (which we had been doing) and model READ_REGISTER as reading (which we had not been doing). Fix this, and also the way that the chain operands were generated at the SDAG level. Patch by Nicholas Paul Johnson, thanks! Test case by me. llvm-svn: 237584
* Revert r237579, as it broke windows buildbotsOliver Stannard2015-05-187-612/+20
| | | | llvm-svn: 237583
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-183-8/+87
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-185-15/+69
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-185-20/+92
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* [LLVM - ARM/AArch64] Add ACLE special register intrinsicsOliver Stannard2015-05-187-20/+612
| | | | | | | | | | | | | | | | | | | This patch implements LLVM support for the ACLE special register intrinsics in section 10.1, __arm_{w,r}sr{,p,64}. This patch is intended to lower the read/write_register instrinsics, used to implement the special register intrinsics in the clang patch for special register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor registers in AArch32 and AArch64. This is done by inspecting the register string passed to the intrinsic and then lowering to the appropriate instruction. Patch by Luke Cheeseman. Differential Revision: http://reviews.llvm.org/D9699 llvm-svn: 237579
* [DAGCombine] Be more pedantic about use iteration in ↵Hal Finkel2015-05-181-11/+12
| | | | | | | | | | | | | | | | | | | | | | | CombineToPreIndexedLoadStore In CombineToPreIndexedLoadStore, when the offset is a constant, we have code that looks for other uses of the pointer which are constant offset computations so that they can be rewritten in terms of the updated pointer so that we don't need to keep a copy of the base pointer to compute these constant offsets. Unfortunately, when it iterated over the uses, it did so by SDNodes, and so we could confuse ourselves if the base pointer was produced by a node that had multiple results (because we would not immediately exclude uses of the other node results). This was reported as PR22755. Unfortunately, we don't have a test case (and I've also been unable to produce one thus far), but at least the mistake is clear. The right way to fix this problem is to make use of the information contained in the use iterators to filter out any uses of other results of the node producing the base pointer. This should be mostly NFC, but should also fix PR22755 (for which, unfortunately, we have no in-tree test case). llvm-svn: 237576
* [LoopAccesses] If shouldRetryWithRuntimeCheck, reset InterestingDependencesAdam Nemet2015-05-181-2/+7
| | | | | | | | When dependence analysis encounters a non-constant distance between memory accesses it aborts the analysis and falls back to run-time checks only. In this case we weren't resetting the array of dependences. llvm-svn: 237574
* [LoopAccesses] Rearrange printed lines in -analyzeAdam Nemet2015-05-181-4/+4
| | | | | | | "Store to invariant address..." is moved as the last line. This is not the prime result of the analysis. Plus it simplifies some of the tests. llvm-svn: 237573
* [LoopAccesses] Debug improvementAdam Nemet2015-05-181-0/+1
| | | | | | Report pointers with unknown bounds. llvm-svn: 237572
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-183-4/+59
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/DElena Demikhovsky2015-05-182-2/+27
| | | | | | | | | instructions. These intrinsics are comming with rounding mode. Added intrinsics for MAXSS/D, MINSS/D - with and without sae. By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 237560
* fixed compilation warning/errorElena Demikhovsky2015-05-181-0/+1
| | | | llvm-svn: 237559
* AVX-512: Added patterns for scalar-to-vector broadcastElena Demikhovsky2015-05-181-0/+10
| | | | llvm-svn: 237558
* AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other ↵Elena Demikhovsky2015-05-183-12/+61
| | | | | | | | instructions from this set Added encoding tests. llvm-svn: 237557
* [PowerPC] Add extra r2 read deps on @toc@l relocationsHal Finkel2015-05-184-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If some commits are happy, and some commits are sad, this is a sad commit. It is sad because it restricts instruction scheduling to work around a binutils linker bug, and moreover, one that may never be fixed. On 2012-05-21, GCC was updated not to produce code triggering this bug, and now we'll do the same... When resolving an address using the ELF ABI TOC pointer, two relocations are generally required: one for the high part and one for the low part. Only the high part generally explicitly depends on r2 (the TOC pointer). And, so, we might produce code like this: .Ltmp526: addis 3, 2, .LC12@toc@ha .Ltmp1628: std 2, 40(1) ld 5, 0(27) ld 2, 8(27) ld 11, 16(27) ld 3, .LC12@toc@l(3) rldicl 4, 4, 0, 32 mtctr 5 bctrl ld 2, 40(1) And there is nothing wrong with this code, as such, but there is a linker bug in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will misoptimize this code sequence to this: nop std r2,40(r1) ld r5,0(r27) ld r2,8(r27) ld r11,16(r27) ld r3,-32472(r2) clrldi r4,r4,32 mtctr r5 bctrl ld r2,40(r1) because the linker does not know (and does not check) that the value in r2 changed in between the instruction using the .LC12@toc@ha (TOC-relative) relocation and the instruction using the .LC12@toc@l(3) relocation. Because it finds these instructions using the relocations (and not by scanning the instructions), it has been asserted that there is no good way to detect the change of r2 in between. As a result, this bug may never be fixed (i.e. it may become part of the definition of the ABI). GCC was updated to add extra dependencies on r2 to instructions using the @toc@l relocations to avoid this problem, and we'll do the same here. This is done as a separate pass because: 1. These extra r2 dependencies are not really properties of the instructions, but rather due to a linker bug, and maybe one day we'll be able to get rid of them when targeting linkers without this bug (and, thus, keeping the logic centralized here will make that straightforward). 2. There are ISel-level peephole optimizations that propagate the @toc@l relocations to some user instructions, and so the exta dependencies do not apply only to a fixed set of instructions (without undesirable definition replication). The test case was reduced with the help of bugpoint, with minimal cleaning. I'm looking forward to our upcoming MI serialization support, and with that, much better tests can be created. llvm-svn: 237556
* MachineScheduler debug output clarity.Andrew Trick2015-05-171-2/+3
| | | | llvm-svn: 237545
* RegisterPressureTracker: reword stale comments.Andrew Trick2015-05-172-9/+13
| | | | llvm-svn: 237544
* Reapply r237520 with another fix for infinite loopingJames Molloy2015-05-175-7/+63
| | | | | | | | | SimplifyDemandedBits was "simplifying" a constant by removing just sign bits. This caused a canonicalization race between different parts of instcombine. Fix and regression test added - third time lucky? llvm-svn: 237539
* AVX-512: fixed extended load to 512-bit registerElena Demikhovsky2015-05-171-2/+2
| | | | llvm-svn: 237537
* AVX-512: fixed a bug in mask operations - (i1 1) patternElena Demikhovsky2015-05-171-2/+2
| | | | | | | Filling k-reg with all-ones value was wrong, (i1 1) should switch on only one bit in mask register llvm-svn: 237536
* Code cleanup: Reindent Fuzzer::MutateAndTestOne.Logan Chien2015-05-171-2/+2
| | | | llvm-svn: 237533
* Revert commits r237521 and r237520.James Molloy2015-05-164-56/+7
| | | | | | | | The AArch64 LNT bot is unhappy - I've found that the problem is in SimpliftDemandedBits, but that's going to require another code review so reverting in the meantime. llvm-svn: 237528
* Move Pass into anonymous namespace. NFC.Benjamin Kramer2015-05-161-0/+2
| | | | llvm-svn: 237526
* [WinEH] Push unique_ptr through the Action interface.Benjamin Kramer2015-05-162-38/+32
| | | | | | | This was the source of many leaks in the past, this should fix them once and for all. llvm-svn: 237524
* Reapply r237453 with a fix for the test timeouts.James Molloy2015-05-164-7/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The test timeouts were due to instcombine fighting itself. Regression test added. Original log message: Canonicalize min/max expressions correctly. This patch introduces a canonical form for min/max idioms where one operand is extended or truncated. This often happens when the other operand is a constant. For example: %1 = icmp slt i32 %a, i32 0 %2 = sext i32 %a to i64 %3 = select i1 %1, i64 %2, i64 0 Would now be canonicalized into: %1 = icmp slt i32 %a, i32 0 %2 = select i1 %1, i32 %a, i32 0 %3 = sext i32 %2 to i64 This builds upon a patch posted by David Majenemer (https://www.marc.info/?l=llvm-commits&m=143008038714141&w=2). That pass passively stopped instcombine from ruining canonical patterns. This patch additionally actively makes instcombine canonicalize too. Canonicalization of expressions involving a change in type from int->fp or fp->int are not yet implemented. llvm-svn: 237520
* [x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.Daniel Sanders2015-05-162-3/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'o' and 'v' are not tested but were already implemented. I'm not sure why 'i' is required for X86 since it's supposed to be an immediate constraint rather than a memory constraint. A test asserts without it so I've included it for now. No functional change intended. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8254 llvm-svn: 237517
* [TableGen] Change 'car' to 'head' and 'cdr' to 'tail' in assert comments. ↵Craig Topper2015-05-161-2/+2
| | | | | | These were the old names for these operations long ago. NFC llvm-svn: 237514
* [TableGen] Remove !! that I can't really explain why I wrote. Also remove ↵Craig Topper2015-05-161-6/+4
| | | | | | some unnecessary curly braces from the same area. llvm-svn: 237513
* Correct indentation. NFCCraig Topper2015-05-161-2/+2
| | | | llvm-svn: 237512
* [TableGen] Restructure a loop to make it exit early instead of skipping a ↵Craig Topper2015-05-161-5/+6
| | | | | | portion of the body based on what will also be the terminating condition. NFC llvm-svn: 237511
* MachineSink: Collect registers before clearing their killflags.Matthias Braun2015-05-161-1/+10
| | | | | | | | | | | | | | | | Currently whenever we sink any instruction, we do clearKillFlags for every use of every use operand for that instruction, apparently there are a lot of duplication, therefore compile time penalties. This patch collect all the interested registers first, do clearKillFlags for it all together at once at the end, so we only need to do clearKillFlags once for one register, duplication is avoided. Patch by Lawrence Hu! Differential Revision: http://reviews.llvm.org/D9719 llvm-svn: 237510
* [MemCpyOpt] Turn memcpy from just-memset'd source into memset.Ahmed Bougacha2015-05-161-1/+45
| | | | | | | | | | | | | | | | | | | There's no point in copying around constants, so, when all else fails, we can still transform memcpy of memset into two independent memsets. To quote the example, we can turn: memset(dst1, c, dst1_size); memcpy(dst2, dst1, dst2_size); into: memset(dst1, c, dst1_size); memset(dst2, c, dst2_size); When dst2_size <= dst1_size. Like r235232 for copy constructors, this can occur in move constructors. Differential Revision: http://reviews.llvm.org/D9682 llvm-svn: 237506
* [MemCpyOpt] Remove dead argument. NFC.Ahmed Bougacha2015-05-161-6/+4
| | | | llvm-svn: 237503
* MC: Use MCSymbol in RelAndSymbol, NFCDuncan P. N. Exon Smith2015-05-165-23/+15
| | | | | | Switch from `MCSymbolData` to `MCSymbol`. llvm-svn: 237502
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-164-2/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. Appropriate tests have been added. There is a companion patch to clang for the rest of this support. llvm-svn: 237499
* MC: Use MCSymbol in MCObject::IsSymbolRefDifferenceFullyResolvedImpl()Duncan P. N. Exon Smith2015-05-165-21/+20
| | | | | | | | Transition one API from `MCSymbolData` to `MCSymbol`. The function needs both, and the backpointer from `MCSymbolData` to `MCSymbol` is going away. llvm-svn: 237498
* MC: Change MCFragment::Atom to an MCSymbol, NFCDuncan P. N. Exon Smith2015-05-165-42/+46
| | | | | | | Change `MCFragment::Atom` from an `MCSymbolData` to an `MCSymbol`, moving in the direction of removing the back-pointer. llvm-svn: 237497
* MC: Change MCAssembler::Symbols to store MCSymbol, NFCDuncan P. N. Exon Smith2015-05-164-16/+15
| | | | | | | | Instead of storing a list of the `MCSymbolData` in use, store the `MCSymbol`s. Churning in the direction of removing the back pointer from `MCSymbolData`. llvm-svn: 237496
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