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* [TableGen] Emit the correct error message.Davide Italiano2015-07-271-1/+1
| | | | llvm-svn: 243284
* Revert "Add const to a bunch of Type* in DataLayout. NFC."Pete Cooper2015-07-271-13/+13
| | | | | | | | This reverts commit r243135. Feedback from Craig Topper and David Blaikie was that we don't put const on Type as it has no mutable state. llvm-svn: 243283
* Revert "Add const to some Type* parameters which didn't need to be mutable. ↵Pete Cooper2015-07-272-10/+10
| | | | | | | | | | NFC." This reverts commit r243146. Feedback from Craig Topper and David Blaikie was that we don't put const on Type as it has no mutable state. llvm-svn: 243282
* [PeepholeOptimizer] Look through PHIs to find additional register sourcesBruno Cardoso Lopes2015-07-272-83/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reapply r242295 with fixes in the implementation. - Teaches the ValueTracker in the PeepholeOptimizer to look through PHI instructions. - Add findNextSourceAndRewritePHI method to lookup into multiple sources returnted by the ValueTracker and rewrite PHIs with new sources. With these changes we can find more register sources and rewrite more copies to allow coaslescing of bitcast instructions. Hence, we eliminate unnecessary VR64 <-> GR64 copies in x86, but it could be extended to other archs by marking "isBitcast" on target specific instructions. The x86 example follows: A: psllq %mm1, %mm0 movd %mm0, %r9 jmp C B: por %mm1, %mm0 movd %mm0, %r9 jmp C C: movd %r9, %mm0 pshufw $238, %mm0, %mm0 Becomes: A: psllq %mm1, %mm0 jmp C B: por %mm1, %mm0 jmp C C: pshufw $238, %mm0, %mm0 Differential Revision: http://reviews.llvm.org/D11197 rdar://problem/20404526 llvm-svn: 243271
* [ARM/AArch64] Fix cost model for interleaved accessesSilviu Baranga2015-07-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Fix the cost of interleaved accesses for ARM/AArch64. We were calling getTypeAllocSize and using it to check the number of bits, when we should have called getTypeAllocSizeInBits instead. This would pottentially cause the vectorizer to generate loads/stores and shuffles which cannot be matched with an interleaved access instruction. No performance changes are expected for now since matching/generating interleaved accesses is still disabled by default. Reviewers: rengolin Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11524 llvm-svn: 243270
* [X86] Reordered lowerVectorShuffleAsBitMask before ↵Simon Pilgrim2015-07-271-86/+86
| | | | | | | | lowerVectorShuffleAsBlend. NFCI. Allows us to show diffs for D11518 more clearly llvm-svn: 243264
* AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaroundMarek Olsak2015-07-271-2/+2
| | | | | | This is a candidate for 3.7. llvm-svn: 243263
* LoopAccessAnalysis.cpp: Tweak r243239 to avoid side effects. It caused ↵NAKAMURA Takumi2015-07-271-3/+4
| | | | | | different emissions between gcc and clang. llvm-svn: 243258
* Avoid using uncommon acronym "MSROM".Sean Silva2015-07-271-2/+2
| | | | llvm-svn: 243256
* Roll forward r243250Jingyue Wu2015-07-262-4/+3
| | | | | | | | | r243250 appeared to break clang/test/Analysis/dead-store.c on one of the build slaves, but I couldn't reproduce this failure locally. Probably a false positive as I saw this test was broken by r243246 or r243247 too but passed later without people fixing anything. llvm-svn: 243253
* Revert r243250Jingyue Wu2015-07-262-3/+4
| | | | | | breaks tests llvm-svn: 243251
* [TTI/CostModel] improve TTI::getGEPCost and use it in ↵Jingyue Wu2015-07-262-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CostModel::getInstructionCost Summary: This patch updates TargetTransformInfoImplCRTPBase::getGEPCost to consider addressing modes. It now returns TCC_Free when the GEP can be completely folded to an addresing mode. I started this patch as I refactored SLSR. Function isGEPFoldable looks common and is indeed used by some WIP of mine. So I extracted that logic to getGEPCost. Furthermore, I noticed getGEPCost wasn't directly tested anywhere. The best testing bed seems CostModel, but its getInstructionCost method invokes getAddressComputationCost for GEPs which provides very coarse estimation. So this patch also makes getInstructionCost call the updated getGEPCost for GEPs. This change inevitably breaks some tests because the cost model changes, but nothing looks seriously wrong -- if we believe the new cost model is the right way to go, these tests should be updated. This patch is not perfect yet -- the comments in some tests need to be updated. I want to know whether this is a right approach before fixing those details. Reviewers: chandlerc, hfinkel Subscribers: aschwaighofer, llvm-commits, aemerson Differential Revision: http://reviews.llvm.org/D9819 llvm-svn: 243250
* Implemented encoding and intrinsics of the following instructionsIgor Breger2015-07-263-96/+134
| | | | | | | | | | vunpckhps/pd, vunpcklps/pd, vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11509 llvm-svn: 243246
* [LAA] Begin moving the logic of generating checks out of addRuntimeCheckAdam Nemet2015-07-261-69/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is to start moving us closer to the model where RuntimePointerChecking will compute and store the checks. Then a client can filter the check according to its requirements and then use the filtered list of checks with addRuntimeCheck. Before the patch, this is all done in addRuntimeCheck. So the patch starts to split up addRuntimeCheck while providing the old API under what's more or less a wrapper now. The new underlying addRuntimeCheck takes a collection of checks now, expands the code for the bounds then generates the code for the checks. I am not completely happy with making expandBounds static because now it needs so many explicit arguments but I don't want to make the type PointerBounds part of LAI. This should get fixed when addRuntimeCheck is moved to LoopVersioning where it really belongs, IMO. Audited the assembly diff of the testsuite (including externals). There is a tiny bit of assembly churn that is due to the different order the code for the bounds is expanded now (MultiSource/Benchmarks/Prolangs-C/bison/conflicts.s and with LoopDist on 456.hmmer/fast_algorithms.s). Reviewers: hfinkel Subscribers: klimek, llvm-commits Differential Revision: http://reviews.llvm.org/D11205 llvm-svn: 243239
* [InstCombine][SSE4A] Standardized references to Length/Width and Index/Start ↵Simon Pilgrim2015-07-251-34/+31
| | | | | | to match AMD docs. NFCI. llvm-svn: 243226
* [LoopUnswitch] Improve loop unswitch pass to find trivial unswitch ↵Chen Li2015-07-251-20/+60
| | | | | | | | | | | | | | | | | conditions more effectively Summary: This patch improves trivial loop unswitch. The current trivial loop unswitch only checks if loop header's terminator contains a trivial unswitch condition. But if the loop header only has one reachable successor (due to intentionally or unintentionally missed code simplification), we should consider the successor as part of the loop header. Therefore, instead of stopping at loop header's terminator, we should keep traversing its successors within loop until reach a *real* conditional branch or switch (whose condition can not be constant folded). This change will enable a single -loop-unswitch pass to unswitch multiple trivial conditions (unswitch one trivial condition could open opportunity to unswitch another one in the same loop), while the old implementation can unswitch only one per pass. Reviewers: reames, broune Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11481 llvm-svn: 243203
* [AArch64][FastISel] Always use an AND instruction when truncating to ↵Juergen Ributzka2015-07-251-31/+24
| | | | | | | | | | | | | | non-legal types. When truncating to non-legal types (such as i16, i8 and i1) always use an AND instruction to mask out the upper bits. This was only done when the source type was an i64, but not when the source type was an i32. This commit fixes this and adds the missing i32 truncate tests. This fixes rdar://problem/21990703. llvm-svn: 243198
* Fix PPCMaterializeInt to check the size of the integer based on theEric Christopher2015-07-251-9/+14
| | | | | | | | | | extension property we're requesting - zero or sign extended. This fixes cases where we want to return a zero extended 32-bit -1 and not be sign extended for the entire register. Also updated the already out of date comment with the current behavior. llvm-svn: 243192
* PPCMaterializeInt should only take a ConstantInt so represent this in the ↵Eric Christopher2015-07-251-12/+9
| | | | | | | | prototype and fix up all uses. llvm-svn: 243191
* [AArch64] Define subtarget feature "reserve-x18", which is used to decideAkira Hatanaka2015-07-254-10/+18
| | | | | | | | | | | | | | | | | whether register x18 should be reserved. This change is needed because we cannot use a backend option to set cl::opt "aarch64-reserve-x18" when doing LTO. Out-of-tree projects currently using cl::opt option "-aarch64-reserve-x18" to reserve x18 should make changes to add subtarget feature "reserve-x18" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11463 llvm-svn: 243186
* DI/Verifier: Fix argument bitrot in DILocalVariableDuncan P. N. Exon Smith2015-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add a verifier check that `DILocalVariable`s of tag `DW_TAG_arg_variable` always have a non-zero 'arg:' field, and those of tag `DW_TAG_auto_variable` always have a zero 'arg:' field. These are the only configurations that are properly understood by the backend. (Also, fix the bad examples in LangRef and test/Assembler, and fix the bug in Kaleidoscope Ch8.) A large number of testcases seem to have bitrotted their way forward from some ancient version of the debug info hierarchy that didn't have `arg:` parameters. If you have out-of-tree testcases that start failing in the verifier and you don't care enough to get the `arg:` right, you may have some luck just calling: sed -e 's/, arg: 0/, arg: 1/' or some such, but I hand-updated the ones in tree. llvm-svn: 243183
* MIR Serialization: Serialize MachineFrameInfo's callee saved information.Alex Lorenz2015-07-242-15/+60
| | | | | | | | | This commit serializes the callee saved information from the class 'MachineFrameInfo'. This commit extends the YAML mappings for the fixed and the ordinary stack objects and adds an optional 'callee-saved-register' attribute. This attribute is used to serialize the callee save information. llvm-svn: 243173
* Handle loop with negtive induction variable incrementLawrence Hu2015-07-241-37/+35
| | | | | | | | | | | | | This patch extend LoopReroll pass to hand the loops which is similar to the following: while (len > 1) { sum4 += buf[len]; sum4 += buf[len-1]; len -= 2; } llvm-svn: 243171
* Remove unnecessary null check. NFC.Pete Cooper2015-07-241-3/+0
| | | | | | | | Since both places which set this variable do so with dyn_cast, and not dyn_cast_or_null, its impossible to get a nullptr here, so we can remove the check. llvm-svn: 243167
* Use make_range(rbegin(), rend()) to allow foreach loops. NFC.Pete Cooper2015-07-2410-39/+26
| | | | | | | | | | | Instead of the pattern for (auto I = x.rbegin(), E = x.end(); I != E; ++I) we can use make_range to construct the reverse range and iterate using that instead. llvm-svn: 243163
* DI: Remove unnecessary DICompositeTypeBaseDuncan P. N. Exon Smith2015-07-241-2/+1
| | | | | | | | | | | | Remove unnecessary and confusing common base class for `DICompositeType` and `DISubroutineType`. While at a high-level `DISubroutineType` is a sort of composite of other types, it has no shared code paths, and its fields are completely disjoint. This relationship was left over from the old debug info hierarchy. llvm-svn: 243160
* DI: Simplify DebugInfoFinder::processType(), NFCDuncan P. N. Exon Smith2015-07-241-7/+9
| | | | | | | | | | | Handle `DISubroutineType` up-front rather than as part of a branch for `DICompositeTypeBase`. The only shared code path was looking through the base type, but `DISubroutineType` can never have a base type. This also removes the last use of `DICompositeTypeBase`, since we can strengthen the cast to `DICompositeType`. llvm-svn: 243159
* DI: Remove dead code: getDICompositeType()Duncan P. N. Exon Smith2015-07-241-15/+0
| | | | llvm-svn: 243158
* AsmPrinter: Use DICompositeType in updateAcceleratorTables(), NFCDuncan P. N. Exon Smith2015-07-241-1/+1
| | | | | | | | `DISubroutineType` is impossible at this `dyn_cast` site, since we're only dealing with named types and `DISubroutineType` cannot be named. Strengthen the `dyn_cast` to `DICompositeType`. llvm-svn: 243157
* MIR Serialization: Serialize the simple virtual register allocation hints.Alex Lorenz2015-07-242-12/+27
| | | | | | | This commit serializes the virtual register allocations hints of type 0. These hints specify the preferred physical registers for allocations. llvm-svn: 243156
* DI: Remove DIDerivedTypeBaseDuncan P. N. Exon Smith2015-07-241-13/+11
| | | | | | | | | Remove an unnecessary (and confusing) common subclass for `DIDerivedType` and `DICompositeType`. These classes aren't really related, and even in the old debug info hierarchy, there was a long-standing FIXME to separate them. llvm-svn: 243152
* Verifier: Sink filename check into visitMDCompositeType(), NFCDuncan P. N. Exon Smith2015-07-241-19/+6
| | | | | | | | We really only want to check this for unions and classes (all the other tags have been ruled out), so simplify the check and move it to the right place. llvm-svn: 243150
* Verifier: Remove unnecessary references to DW_TAG_subroutine_type, NFCDuncan P. N. Exon Smith2015-07-241-2/+0
| | | | | | | | | Remove unnecessary references to `DW_TAG_subroutine_type` in `visitDICompositeType()` and `visitDIDerivedTypeBase()`, since `visitDISubroutineType()` doesn't call either of those (and shouldn't, since subroutine types are really quite special). llvm-svn: 243149
* DI: Clarify isUnsignedDIType(), NFCDuncan P. N. Exon Smith2015-07-241-17/+18
| | | | | | | | | | | | Refactor `isUnsignedDIType()` to deal with `DICompositeType` explicitly. Since `DW_TAG_subroutine_type` isn't handled here (the assertions about tags rule it out), this allows strengthening the `dyn_cast` to `DIDerivedType`. Besides making the code clearer, this it removes a use of `DIDerivedTypeBase`. llvm-svn: 243148
* Add const to some Type* parameters which didn't need to be mutable. NFC.Pete Cooper2015-07-242-10/+10
| | | | | | | We were only getting the size of the type which doesn't need to modify the type. llvm-svn: 243146
* Remove unused variable. NFC.Diego Novillo2015-07-241-1/+0
| | | | llvm-svn: 243145
* DI: Strengthen some dyn_casts to DIDerivedType, NFCDuncan P. N. Exon Smith2015-07-241-2/+2
| | | | | | | | The surrounding code proves in both cases that these must be `DIDerivedType` if they're `DIDerivedTypeBase`, so strengthen the `dyn_cast`s to the more specific type. llvm-svn: 243143
* Remove the user-count threshold when analyzing read attributesJingyue Wu2015-07-241-3/+0
| | | | | | | | | | | | | | | | | | | | | | | Summary: This threshold limited FunctionAttrs ability to prove arguments to be read-only. In NVPTX, a specialized instruction ld.global.nc can be used to load memory with non-coherent texture cache. We notice that in SHOC [1] benchmark, some function arguments are not marked with readonly because FunctionAttrs reaches a hardcoded threshold when analysis uses. Removing this threshold won't cause significant regression in compilation time, because the worst-case time complexity of the algorithm is still O(# of instructions) for each parameter. Patched by Xuetian Weng. [1] https://github.com/vetter/shoc Reviewers: nlewycky, jingyue, nicholas Subscribers: nicholas, test, llvm-commits Differential Revision: http://reviews.llvm.org/D11311 llvm-svn: 243141
* [RewriteStatepointsForGC] Adjust naming scheme to be more stablePhilip Reames2015-07-241-3/+7
| | | | | | The names for instructions inserted were previous dependent on iteration order. By deriving the names from the original instructions, we can avoid instability in tests without resorting to ordered traversals. It also makes the IR mildly easier to read at large scale. llvm-svn: 243140
* DI: Strengthen block-byref cast to DIDerivedType, NFCDuncan P. N. Exon Smith2015-07-241-1/+1
| | | | | | | This code is visiting the members of a block-byref, and we know those are all `DIDerivedType`. Strengthen the cast. llvm-svn: 243138
* Use foreach loops for StructType::elements(). NFC.Pete Cooper2015-07-243-8/+8
| | | | | | | | | | | | We had a few places where we did for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { but those could instead do for (auto *EltTy : STy->elements()) { llvm-svn: 243136
* Add const to a bunch of Type* in DataLayout. NFC.Pete Cooper2015-07-241-13/+13
| | | | | | | | Almost all methods in DataLayout took mutable pointers but didn't need to. These were only accessing constant methods of the types, or using the Type* to key a map. Neither of these needs a mutable pointer. llvm-svn: 243135
* DI: Only DICompositeType has getElements(), NFCDuncan P. N. Exon Smith2015-07-242-2/+2
| | | | | | | | There is an assertion inside `DICompositeTypeBase::getElements()` that `this` is not a `DISubroutineType`, leaving only `DICompositeType`. Make that clear at the call sites. llvm-svn: 243134
* MIR Parser: Run the machine verifier after initializing machine functions.Alex Lorenz2015-07-241-0/+4
| | | | llvm-svn: 243128
* [RuntimeDyld] MachO: Add support for ARM scattered vanilla relocations.Lang Hames2015-07-244-38/+46
| | | | llvm-svn: 243126
* AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer ↵Igor Breger2015-07-246-108/+522
| | | | | | | | | | Truncate with/without saturation Added tests for DAG lowering ,encoding and intrinsic Differential Revision: http://reviews.llvm.org/D11218 llvm-svn: 243122
* Remove access to the DataLayout in the TargetMachineMehdi Amini2015-07-249-31/+36
| | | | | | | | | | | | | | | | | | | | | | Summary: Replace getDataLayout() with a createDataLayout() method to make explicit that it is intended to create a DataLayout only and not accessing it for other purpose. This change is the last of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11103 (cherry picked from commit 5609fc56bca971e5a7efeaa6ca4676638eaec5ea) From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243114
* fix wrong comment; NFCSanjay Patel2015-07-241-1/+1
| | | | llvm-svn: 243113
* [ARM] - Fix lowering of shufflevectors in AArch32Luke Cheeseman2015-07-241-38/+127
| | | | | | | | | | | | | | | | | | | Some shufflevectors are currently being incorrectly lowered in the AArch32 backend as the existing checks for detecting the NEON operations from the shufflevector instruction expects the shuffle mask and the vector operands to be of the same length. This is not always the case as the mask may be twice as long as the operand; here only the lower half of the shufflemask gets checked, so provided the lower half of the shufflemask looks like a vector transpose (or even is just all -1 for undef) then the intrinsics may get incorrectly lowered into a vector transpose (VTRN) instruction. This patch fixes this by accommodating for both cases and adds regression tests. Differential Revision: http://reviews.llvm.org/D11407 llvm-svn: 243103
* When lowering vector shifts a check is performed to see if the value to shift byLuke Cheeseman2015-07-242-17/+14
| | | | | | | | | | | | is an immediate, in this check the value is negated and stored in and int64_t. The value can be -2^63 yet the result cannot be stored in an int64_t and this gives some undefined behaviour causing failures. The negation is only necessary when the values is within a certain range and so it should not need to negate -2^63, this patch introduces this and also a regression test. Differential Revision: http://reviews.llvm.org/D11408 llvm-svn: 243100
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