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llvm-svn: 122408
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llvm-svn: 122407
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llvm-svn: 122406
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llvm-svn: 122405
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llvm-svn: 122404
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RecordRelocation with lots of FIXMEs.
llvm-svn: 122402
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llvm-svn: 122401
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clear how to keep in the generic path (yet).
- Will revisit when it actually works.
llvm-svn: 122400
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if both A op B and A op C simplify. This fires fairly often but doesn't
make that much difference. On gcc-as-one-file it removes two "and"s and
turns one branch into a select.
llvm-svn: 122399
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llvm-svn: 122398
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instcombine is compared to instsimplify.
llvm-svn: 122397
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loads properly. We miscompiled the testcase into:
_test: ## @test
movl $128, (%rdi)
movzbl 1(%rdi), %eax
ret
Now we get a proper:
_test: ## @test
movl $128, (%rdi)
movsbl (%rdi), %eax
movzbl %ah, %eax
ret
This fixes PR8757.
llvm-svn: 122392
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unhanded cases faster and simplify code.
llvm-svn: 122391
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llvm-svn: 122389
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llvm-svn: 122385
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llvm-svn: 122384
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llvm-svn: 122381
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llvm-svn: 122379
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conditional branch values.
I still think that LVI should be handling this, but that capability is some ways off in the future,
and this matters for some significant benchmarks.
llvm-svn: 122378
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types, but they're just getting converted to unsigned anyway, so cast first
(and ask questions later).
llvm-svn: 122377
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llvm-svn: 122371
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the same physical register. Simplifies the fix from the previous
checkin r122211.
llvm-svn: 122370
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llvm-svn: 122368
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the shift type was needed one place, the shift count
type another. The transform in 123555 had the same
problem.
llvm-svn: 122366
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(add Y, (sete X, 0)) -> cmp X, 1; adc 0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete X, 0), Y) -> cmp X, 1; sbb 0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y
for
unsigned foo(unsigned a, unsigned b) {
if (a == 0) b++;
return b;
}
we now get:
foo:
cmpl $1, %edi
movl %esi, %eax
adcl $0, %eax
ret
instead of:
foo:
testl %edi, %edi
sete %al
movzbl %al, %eax
addl %esi, %eax
ret
llvm-svn: 122364
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while at it.
llvm-svn: 122362
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llvm-svn: 122360
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the folding it can.
llvm-svn: 122359
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are not actually relaxed. For example, a section with only alignments will never
needs relaxation.
llvm-svn: 122356
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llvm-svn: 122355
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count operand. These should be the same but apparently are
not always, and this is cleaner anyway. This improves the
code in an existing test.
llvm-svn: 122354
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llvm-svn: 122353
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llvm-svn: 122349
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llvm-svn: 122345
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visit instructions before their uses, since InstructionSimplify does a
better job in that case. All this prompted by Frits van Bommel.
llvm-svn: 122343
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llvm-svn: 122342
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not very important since the pass is only used for testing, but it does make
it more realistic. Suggested by Frits van Bommel.
llvm-svn: 122336
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type.
llvm-svn: 122334
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not assume this (for example in case more transforms get added below
it). Suggested by Frits van Bommel.
llvm-svn: 122332
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llvm-svn: 122331
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plenty left though!), in particular for multiplication.
llvm-svn: 122330
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quite often, but don't make much difference in practice presumably because
instcombine also knows them and more.
llvm-svn: 122328
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No functionality change.
llvm-svn: 122327
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a couple of existing transforms. This fires surprisingly often, for
example when compiling gcc "(X+(-1))+1->X" fires quite a lot as well
as various "and" simplifications (usually with a phi node operand).
Most of the time this doesn't make a real difference since the same
thing would have been done elsewhere anyway, eg: by instcombine, but
there are a few places where this results in simplifications that we
were not doing before.
llvm-svn: 122326
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of the problems with my last attempt were in the updating of LiveIntervals
rather than the coalescing itself. Therefore, I decided to get that right first
by essentially reimplementing the existing PHIElimination using LiveIntervals.
It works correctly, with only a few tests failing (which may not be legitimate
failures) and no new verifier failures (at least as far as I can tell, I didn't
count the number per file).
llvm-svn: 122321
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Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register. Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up. Radar 8755338.
llvm-svn: 122319
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section.
This helps because in practice sections form a dag with debug sections pointing
to text sections. Finishing up the text sections first makes the debug section
relaxation trivial.
llvm-svn: 122314
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Fixes rdar://8782223
llvm-svn: 122313
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something that just glues two nodes together, even if it is
sometimes used for flags.
llvm-svn: 122310
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to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.
Fixes part of rdar://8782207
llvm-svn: 122307
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