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* When disabling PRE for a value is directly redundant with itselfDan Gohman2013-02-121-0/+2
| | | | | | | (through a loop), don't continue to iterate through the reamining predecessors. llvm-svn: 174994
* Check that pointers are removed from maps before calling delete on the pointers,Dan Gohman2013-02-121-3/+3
| | | | | | for tidiness' sake. llvm-svn: 174988
* Minor code simplification.Dan Gohman2013-02-121-1/+1
| | | | llvm-svn: 174985
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-121-19/+40
| | | | | | | | | | | | | | This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 llvm-svn: 174983
* Allow optionally generating pubnames section in DWARF info. IntroduceKrzysztof Parzyszek2013-02-125-2/+95
| | | | | | option "generate-dwarf-pubnames" to control it, set to "false" by default. llvm-svn: 174981
* Equal treatment of labels and other terminators in MI DAG construction.Sergei Larin2013-02-121-1/+1
| | | | | | | MI sched DAG construction allows targets to include terminators into scheduling DAG. Extend this functionality to labels as well. llvm-svn: 174977
* Add support for the pubnames section to llvm-dwarfdump.Krzysztof Parzyszek2013-02-122-0/+23
| | | | llvm-svn: 174976
* Hexagon: Add support to generate predicated absolute addressing modeJyotsna Verma2013-02-121-20/+123
| | | | | | instructions. llvm-svn: 174973
* PR14562 - Truncation of left shift became undefPaul Redmond2013-02-121-2/+9
| | | | | | | | | | | DAGCombiner::ReduceLoadWidth was converting (trunc i32 (shl i64 v, 32)) into (shl i32 v, 32) into undef. To prevent this, check the shift count against the final result size. Patch by: Kevin Schoedel Reviewed by: Nadav Rotem llvm-svn: 174972
* [NVPTX] Disable vector registersJustin Holewinski2013-02-1217-1997/+1274
| | | | | | | | | | | Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. llvm-svn: 174968
* [ASan] Do not use kDefaultShort64bitShadowOffset on Mac, where the binaries ↵Alexander Potapenko2013-02-121-1/+2
| | | | | | may get mapped at 0x100000000+ and thus may interleave with the shadow. llvm-svn: 174964
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
| | | | | | | | | | | | | | | 'R600/SI: Use proper instructions for array/shadow samplers.' removed two cases from TEX_SHADOW. Vincent Lejeune reported on IRC that this broke some shadow array piglit tests with the r600g driver. Reinstating the removed cases should fix this, and still works with radeonsi as well. I will follow up with some lit tests which would have caught the regression. NOTE: This is a candidate for the Mesa stable branch. Tested-by: Vincent Lejeune <vljn@ovi.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174963
* [asan] change the default mapping offset on x86_64 to 0x7fff8000. This gives ↵Kostya Serebryany2013-02-121-3/+5
| | | | | | roughly 5% speedup. Since this is an ABI change, bump the asan ABI version by renaming __asan_init to __asan_init_v1. llvm part, compiler-rt part will follow llvm-svn: 174957
* Merge the collected attributes into the call instruction's attributes.Bill Wendling2013-02-121-2/+2
| | | | llvm-svn: 174955
* Have the bitcode writer and reader handle the new attribute references.Bill Wendling2013-02-122-33/+11
| | | | | | | | The bitcode writer emits a reference to the attribute group that the object at the given index refers to. The bitcode reader is modified to read this in and map it back to the attribute group. llvm-svn: 174952
* Use the AttributeSet as the 'key' to the map instead of the 'raw' pointer.Bill Wendling2013-02-122-5/+6
| | | | llvm-svn: 174950
* Support string attributes in the AttrBuilder.Bill Wendling2013-02-121-11/+25
| | | | llvm-svn: 174948
* Don't consider definitions by other PHIs live-in when trimming a PHI source'sCameron Zwarich2013-02-121-1/+5
| | | | | | live range after inserting a copy at the end of a block. llvm-svn: 174945
* Fix indentation.Cameron Zwarich2013-02-121-2/+2
| | | | llvm-svn: 174944
* Add a hidden option to PHIElimination to split all critical edges. This isCameron Zwarich2013-02-121-4/+9
| | | | | | | particularly useful for catching issues with architectures that have exotic terminators like MIPS. llvm-svn: 174938
* Add blocks to the LiveIntervalAnalysis RegMaskBlocks array when splittingCameron Zwarich2013-02-121-2/+6
| | | | | | a critical edge. llvm-svn: 174936
* Fix the updating of LiveIntervals after splitting a critical edge. PHI operandCameron Zwarich2013-02-121-12/+3
| | | | | | | live ranges should always be extended, and the only successor that should be considered for extension of other ranges is the target of the split edge. llvm-svn: 174935
* Check type for legality before forming a select from loads.Pete Cooper2013-02-121-1/+3
| | | | | | | | Sorry for the lack of a test case. I tried writing one for i386 as i know selects are illegal on this target, but they are actually considered legal by isel and expanded later. I can't see any targets to trigger this, but checking for the legality of a node before forming it is general goodness. llvm-svn: 174934
* ARM cost model: Add vector reverse shuffle costsArnold Schwaighofer2013-02-121-0/+33
| | | | | | | | | A reverse shuffle is lowered to a vrev and possibly a vext instruction (quad word). radar://13171406 llvm-svn: 174933
* Cost model: Add check for reverse shuffles to CostModel analysisArnold Schwaighofer2013-02-121-0/+18
| | | | | | | | | | Check for reverse shuffles in the CostModel analysis pass and query TargetTransform info accordingly. This allows us we can write test cases for reverse shuffles. radar://13171406 llvm-svn: 174932
* ARM NEON: Handle v16i8 and v8i16 reverse shufflesArnold Schwaighofer2013-02-121-1/+37
| | | | | | | | | | | | | | | Lower reverse shuffles to a vrev64 and a vext instruction instead of the default legalization of storing and loading to the stack. This is important because we generate reverse shuffles in the loop vectorizer when we reverse store to an array. uint8_t Arr[N]; for (i = 0; i < N; ++i) Arr[N - i - 1] = ... radar://13171760 llvm-svn: 174929
* Update error message due to previous commit, r174926.Chad Rosier2013-02-121-1/+3
| | | | llvm-svn: 174927
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-14/+47
| | | | | | Part of rdar://12470373 llvm-svn: 174926
* DIBuilder: make the return type of createBasicType more specificDavid Blaikie2013-02-121-4/+4
| | | | llvm-svn: 174924
* Added 0x0D to 2-byte opcode extension table for prefetch* variantsKay Tiong Khoo2013-02-121-4/+2
| | | | | | | Fixed decode of existing 3dNow prefetchw instruction Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs llvm-svn: 174920
* BBVectorize: Don't over-search when building the dependency mapHal Finkel2013-02-111-2/+10
| | | | | | | | | | | | | When building the pairable-instruction dependency map, don't search past the last pairable instruction. For large blocks that have been divided into multiple instruction groups, searching past the last instruction in each group is very wasteful. This gives a 32% speedup on the csa.ll test case from PR15222 (when using 50 instructions in each group). No functionality change intended. llvm-svn: 174915
* BBVectorize: Omit unnecessary entries in PairableInstUsersHal Finkel2013-02-111-1/+3
| | | | | | | | | | | This map is queried only for instructions in pairs of pairable instructions; so make sure that only pairs of pairable instructions are added to the map. This gives a 3.5% speedup on the csa.ll test case from PR15222. No functionality change intended. llvm-svn: 174914
* [mips] Expand pseudo instructions before they are emitted inAkira Hatanaka2013-02-111-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | MipsCodeEmitter.cpp. JALR and NOP are expanded by function emitPseudoExpansionLowering, which is not called when the old JIT is used. This fixes the following tests which have been failing on llvm-mips-linux builder: LLVM :: ExecutionEngine__2003-01-04-LoopTest.ll LLVM :: ExecutionEngine__2003-05-06-LivenessClobber.ll LLVM :: ExecutionEngine__2003-06-04-bzip2-bug.ll LLVM :: ExecutionEngine__2005-12-02-TailCallBug.ll LLVM :: ExecutionEngine__2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll LLVM :: ExecutionEngine__hello2.ll LLVM :: ExecutionEngine__stubs.ll LLVM :: ExecutionEngine__test-branch.ll LLVM :: ExecutionEngine__test-call.ll LLVM :: ExecutionEngine__test-common-symbols.ll LLVM :: ExecutionEngine__test-loadstore.ll LLVM :: ExecutionEngine__test-loop.ll llvm-svn: 174912
* Rename AttributeSets to AttributeGroups so that it's more meaningful.Bill Wendling2013-02-113-41/+41
| | | | llvm-svn: 174911
* Use a std::map so that we record the group ID.Bill Wendling2013-02-112-7/+8
| | | | llvm-svn: 174910
* [mips] Fix indentation.Akira Hatanaka2013-02-111-41/+39
| | | | llvm-svn: 174907
* Optimization: bitcast (<1 x ...> insertelement ..., X, ...) to ... ==> ↵Michael Ilseman2013-02-111-5/+16
| | | | | | bitcast X to ... llvm-svn: 174905
* Extend Hexagon hardware loop generation to handle various additional cases:Krzysztof Parzyszek2013-02-114-382/+1470
| | | | | | | | - variety of compare instructions, - loops with no preheader, - arbitrary lower and upper bounds. llvm-svn: 174904
* Implement HexagonInstrInfo::analyzeCompare.Krzysztof Parzyszek2013-02-112-0/+86
| | | | llvm-svn: 174901
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-4/+4
| | | | | | *added file for test cases for i386 intel syntax llvm-svn: 174900
* BBVectorize: Eliminate one more restricted linear searchHal Finkel2013-02-111-27/+31
| | | | | | | | | | This eliminates one more linear search over a range of std::multimap entries. This gives a 22% speedup on the csa.ll test case from PR15222. No functionality change intended. llvm-svn: 174893
* R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.Michel Danzer2013-02-111-15/+9
| | | | | | | | | | | | | The modifiers don't seem to have any effect with V_MOV_B32, supposedly it's meant to just move bits untouched. Fixes 46 piglit tests with radeonsi, though unfortunately 11 of those had just regressed because they started using the clamp modifier. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174890
* [asan] added a flag -mllvm asan-short-64bit-mapping-offset=1 (0 by default)Kostya Serebryany2013-02-111-2/+8
| | | | | | | | | | This flag makes asan use a small (<2G) offset for 64-bit asan shadow mapping. On x86_64 this saves us a register, thus achieving ~2/3 of the zero-base-offset's benefits in both performance and code size. Thanks Jakub Jelinek for the idea. llvm-svn: 174886
* AArch64: fix build on some MSVC versionsTim Northover2013-02-111-3/+3
| | | | | | | | | | | | | | | This does two things: It removes a call to abs() which may have "long long" parameter on Windows, which is not necessarily available in C++03. It also corrects the signedness of Amount, which was relying on implementation-defined conversions previously. Code was already tested (albeit in an implemnetation defined way) so no extra tests. llvm-svn: 174885
* AArch64: Simplify logic in deciding whether bfi is validTim Northover2013-02-111-6/+1
| | | | | | | | Previous code had a confusing comment which was mostly an implementation detail. This condition corresponds to "lsb up to register width" and "width not ridiculous". llvm-svn: 174877
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-112-18/+218
| | | | | | | | | This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. llvm-svn: 174871
* Add support for updating LiveIntervals to ↵Cameron Zwarich2013-02-112-1/+69
| | | | | | | | | | | | | | | MachineBasicBlock::SplitCriticalEdge(). This is currently a bit hairier than it needs to be, since depending on where the split block resides the end ListEntry of the split block may be the end ListEntry of the original block or a new entry. Some changes to the SlotIndexes updating should make it possible to eliminate the two cases here. This also isn't as optimized as it could be. In the future Liveinterval should probably get a flag that indicates whether the LiveInterval is within a single basic block. We could ignore all such intervals when splitting an edge. llvm-svn: 174870
* Update SlotIndexes after updateTerminator() possibly removes instructions. I amCameron Zwarich2013-02-111-0/+24
| | | | | | really trying to avoid piping SlotIndexes through to RemoveBranch() and friends. llvm-svn: 174869
* Add support for printing out the attribute groups.Bill Wendling2013-02-113-17/+88
| | | | | | | | | | | | This emits the attribute groups that are used by the functions. (It currently doesn't print out return type or parameter attributes within attribute groups.) Note: The functions still retrieve their attributes from the "old" bitcode format (using the deprecated 'Raw()' method). This means that string attributes within an attribute group will not show up during a disassembly. This will be addressed in a future commit. llvm-svn: 174867
* [tsan/msan] adding thread_safety and uninitialized_checks attributesKostya Serebryany2013-02-117-3/+19
| | | | llvm-svn: 174864
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