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* [CodeView] Handle Cross Module Imports and Exports.Zachary Turner2017-06-059-19/+329
| | | | | | | | | | | | | | | While it's not entirely clear why a compiler or linker might put this information into an object or PDB file, one has been spotted in the wild which was causing llvm-pdbdump to crash. This patch adds support for reading-writing these sections. Since I don't know how to get one of the native tools to generate this kind of debug info, the only test here is one in which we feed YAML into the tool to produce a PDB and then spit out YAML from the resulting PDB and make sure that it matches. llvm-svn: 304738
* AMDGPU: Remove deprecated and unused elf definitionsKonstantin Zhuravlyov2017-06-056-150/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D33689 llvm-svn: 304737
* CodeGen: add support for emitting ObjC image infoSaleem Abdulrasool2017-06-051-23/+70
| | | | | | | | | This ensures that we can emit the ObjC Image Info structure on COFF and ELF as well. The frontend already would attempt to emit this information but would get dropped when generating assembly or an object file. llvm-svn: 304736
* [ConstantRange] Remove costly udivrem from ConstantRange::truncateCraig Topper2017-06-051-15/+19
| | | | | | | | | | | | Truncate currently uses a udivrem call which is going to be slow particularly for larger than 64-bit widths. As far as I can tell all we were trying to do was modulo LowerDiv by (MaxValue+1) and make sure whatever value was effectively subtracted from LowerDiv was also subtracted from UpperDiv. This patch recognizes that MaxValue+1 is a power of 2 so we can just use a bitwise AND to accomplish a modulo operation or isolate the upper bits. Differential Revision: https://reviews.llvm.org/D32672 llvm-svn: 304733
* [AMDGPU] Fix uninit'ed var (RevisitLoop)Mark Searles2017-06-051-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D33907 llvm-svn: 304729
* [DAGCombine] Fix unchecked calls to DAGCombiner::*ExtPromoteOperandSanjay Patel2017-06-051-6/+6
| | | | | | | | | | | | | | | | | Other calls to DAGCombiner::*PromoteOperand check the result, but here it could cause an assertion in getNode. Falling back to any extend in this case instead of failing outright seems correct to me. No test case because: The failure was triggered by an out of tree backend. In order to trigger it, a backend would need to overload TargetLowering::IsDesirableToPromoteOp to return true for a type for which ISD::SIGN_EXTEND_INREG is marked illegal. In tree, only X86 overloads and sometimes returns true for MVT::i16 yet it marks setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);. Patch by Jacob Young! Differential Revision: https://reviews.llvm.org/D33633 llvm-svn: 304723
* [X86][SSE41] Non-temporal loads shouldn't be folded if it can be avoided ↵Simon Pilgrim2017-06-051-2/+6
| | | | | | | | | | (PR32743) Missed SSE41 non-temporal load case in previous commit Differential Revision: https://reviews.llvm.org/D33728 llvm-svn: 304722
* Handle non-unique edges in edge-dominanceAdam Nemet2017-06-051-13/+7
| | | | | | | | | | | | | | | | | | | | | | | | This removes a quadratic behavior in assert-enabled builds. GVN propagates the equivalence from a condition into the blocks guarded by the condition. E.g. for 'if (a == 7) { ... }', 'a' will be replaced in the block with 7. It does this by replacing all the uses of 'a' that are dominated by the true edge. For a switch with N cases and U uses of the value, this will mean N * U calls to 'dominates'. Asserting isSingleEdge in 'dominates' make this N^2 * U because this function checks for the uniqueness of the edge. I.e. traverses each edge between the SwitchInst's block and the cases. The change removes the assert and makes 'dominates' works correctly in the presence of non-unique edges. This brings build time down by an order of magnitude for an input that has ~10k cases in a switch statement. Differential Revision: https://reviews.llvm.org/D33584 llvm-svn: 304721
* Close DynamicLibraries in reverse order they were opened.Frederich Munch2017-06-052-2/+3
| | | | | | | | | | | | | | Summary: Matches C++ destruction ordering better and fixes possible problems of loaded libraries having inter-dependencies. Reviewers: efriedma, v.g.vassilev, chapuni Reviewed By: efriedma Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D33652 llvm-svn: 304720
* Symbols re-defined with -wrap and -defsym need to be excluded from inter-Dmitry Mikulin2017-06-051-4/+13
| | | | | | | | | | procedural optimizations to prevent dropping symbols and allow the linker to process re-directs. PR33145: --wrap doesn't work with lto. Differential Revision: https://reviews.llvm.org/D33621 llvm-svn: 304719
* [X86][AVX1] Split 256-bit vector non-temporal loads to keep it non-temporal ↵Simon Pilgrim2017-06-051-6/+18
| | | | | | | | (PR32744) Differential Revision: https://reviews.llvm.org/D33728 llvm-svn: 304718
* [X86][SSE] Non-temporal loads shouldn't be folded if it can be avoided (PR32743)Simon Pilgrim2017-06-051-9/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D33728 llvm-svn: 304717
* [ARM] GlobalISel: Constrain callee register on indirect callsDiana Picus2017-06-051-1/+10
| | | | | | | | | | | | | When lowering calls, we generate instructions with machine opcodes rather than generic ones. Therefore, we need to constrain the register classes of the operands. Also enable the machine verifier on the arm-irtranslator.ll test, since that would've caught this issue. Fixes (part of) PR32146. llvm-svn: 304712
* [LLVM-C] [OCaml] Expose Type::subtypes.whitequark2017-06-051-0/+12
| | | | | | | | | | | | | The C functions added are LLVMGetNumContainedTypes and LLVMGetSubtypes. The OCaml function added is Llvm.subtypes. Patch by Ekaterina Vaartis. Differential Revision: https://reviews.llvm.org/D33677 llvm-svn: 304709
* Fix building DynamicLibrary.cpp with musl libcDimitry Andric2017-06-051-2/+2
| | | | | | | | | | | | | | | | | | | | | Summary: The workaround added in rL301240 for stderr/out/in symbols being both macros and globals is only necessary for glibc, and it does not compile with musl libc. Alpine Linux has had the following fix for it: https://git.alpinelinux.org/cgit/aports/plain/main/llvm4/llvm-fix-DynamicLibrary-to-build-with-musl-libc.patch Adapt the fix in our DynamicLibrary.inc for Unix. Reviewers: marsupial, chandlerc, krytarowski Reviewed By: krytarowski Subscribers: srhines, krytarowski, llvm-commits Differential Revision: https://reviews.llvm.org/D33883 llvm-svn: 304707
* Add support for #pragma clang sectionJaved Absar2017-06-053-1/+35
| | | | | | | | | | | | | | | This patch provides a means to specify section-names for global variables, functions and static variables, using #pragma directives. This feature is only defined to work sensibly for ELF targets. One can specify section names as: #pragma clang section bss="myBSS" data="myData" rodata="myRodata" text="myText" One can "unspecify" a section name with empty string e.g. #pragma clang section bss="" data="" text="" rodata="" Reviewers: Roger Ferrer, Jonathan Roelofs, Reid Kleckner Differential Revision: https://reviews.llvm.org/D33413 llvm-svn: 304704
* [ARM] Support fixup for Thumb2 modified immediatePeter Smith2017-06-054-3/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a new fixup fixup_t2_so_imm for the t2_so_imm_asmoperand "T2SOImm". The fixup permits code such as: .L1: sub r3, r3, #.L2 - .L1 .L2: to assemble in Thumb2 as well as in ARM state. The operand predicate isT2SOImm() explicitly doesn't match expressions containing :upper16: and :lower16: as expressions with these operators must match the movt and movw instructions. The test mov r0, foo2 in thumb2-diagnostics is moved to a new file as the fixup delays the error message till after the assembler has quit due to the other errors. As the mov instruction shares the t2_so_imm_asmoperand mov instructions with a non constant expression now match t2MOVi rather than t2MOVi16 so the error message is slightly different. Fixes PR28647 Differential Revision: https://reviews.llvm.org/D33492 llvm-svn: 304702
* [InstCombine] Fix extractelement use before defSven van Haastregt2017-06-051-1/+1
| | | | | | | | | | | | This fixes a bug that can cause extractelements with operands that haven't been defined yet to be inserted at a wrong point when optimising insertelements. Patch by Karl Hylen. Differential Revision: https://reviews.llvm.org/D33449 llvm-svn: 304701
* Revert "[sanitizer-coverage] one more flavor of coverage: ↵Renato Golin2017-06-051-43/+9
| | | | | | | | -fsanitize-coverage=inline-8bit-counters. Experimental so far, not documenting yet." This reverts commit r304630, as it broke ARM/AArch64 bots for 2 days. llvm-svn: 304698
* [AMDGPU] Fix SIFoldOperands crash with clampStanislav Mekhanoshin2017-06-051-1/+2
| | | | | | | | | Fixes bug #33302. Pass did not account that Src1 of max instruction can be an immediate. Differential Revision: https://reviews.llvm.org/D33884 llvm-svn: 304696
* [InstSimplify] Use llvm::all_of instead of a manual loop. NFCCraig Topper2017-06-041-3/+2
| | | | llvm-svn: 304692
* IR: When creating a global variable, assert that its type is valid.Peter Collingbourne2017-06-041-0/+4
| | | | llvm-svn: 304690
* [X86][SSE] Change BUILD_VECTOR interleaving ordering to improve ↵Simon Pilgrim2017-06-041-18/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | coalescing/combine opportunities We currently generate BUILD_VECTOR as a tree of UNPCKL shuffles of the same type: e.g. for v4f32: Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> Step 2: unpcklps X, Y ==> <3, 2, 1, 0> The issue is because we are not placing sequential vector elements together early enough, we fail to recognise many combinable patterns - consecutive scalar loads, extractions etc. Instead, this patch unpacks progressively larger sequential vector elements together: e.g. for v4f32: Step 1: unpcklps 0, 2 ==> X: <?, ?, 1, 0> : unpcklps 1, 3 ==> Y: <?, ?, 3, 2> Step 2: unpcklpd X, Y ==> <3, 2, 1, 0> This does mean that we are creating UNPCKL shuffle of different value types, but the relevant combines that benefit from this are quite capable of handling the additional BITCASTs that are now included in the shuffle tree. Differential Revision: https://reviews.llvm.org/D33864 llvm-svn: 304688
* [LV] Make scalarizeInstruction() non-virtual. NFC.Ayal Zaks2017-06-041-2/+1
| | | | | | | | | | Following the request made in https://reviews.llvm.org/D32871, scalarizeInstruction() which is no longer overridden by InnerLoopUnroller is hereby made non-virtual in InnerLoopVectorizer. Should have been part of r297580 originally. llvm-svn: 304685
* [ConstantFolding] Combine an if statement into an earlier one that checked ↵Craig Topper2017-06-041-7/+3
| | | | | | the same condition. NFC llvm-svn: 304681
* [ConstantFolding][X86] Replace an LLVM_FALLTHROUGH with a break because it ↵Craig Topper2017-06-041-1/+2
| | | | | | | | really shouldn't fallthrough. This is actually NFC because the next case starts with the same if statement as this case did. So the result will be the same and it will fallthrough to the end of the switch. But there's no reason to rely on that so we should just break. llvm-svn: 304680
* [ConstantFolding] Properly support constant folding of vector powi ↵Craig Topper2017-06-041-1/+2
| | | | | | intrinsic. The second argument is not a vector so needs special treatment. llvm-svn: 304679
* [PM] Add GVNSink to the pipeline.Davide Italiano2017-06-031-0/+10
| | | | | | | | | With this, the two pipelines should be in sync again (modulo LoopUnswitch, but Chandler is actively working on that). Differential Revision: https://reviews.llvm.org/D33810 llvm-svn: 304671
* ADT: handle special case of ARM environment for SUSESaleem Abdulrasool2017-06-031-0/+4
| | | | | | | SUSE treats "gnueabi" as "gnueabihf" so make sure that we normalise the environment. llvm-svn: 304670
* [InstCombine] Add support for simplifying ctlz/cttz intrinsics based on ↵Craig Topper2017-06-031-5/+1
| | | | | | known bits. llvm-svn: 304669
* [ConstantFolding] Fix constant folding for vector cttz and ctlz intrinsics ↵Craig Topper2017-06-031-0/+7
| | | | | | to understand that the second argument is still a scalar. llvm-svn: 304668
* [AMDGPU] Untangle SDWA pass from SIShrinkInstructionsStanislav Mekhanoshin2017-06-032-26/+67
| | | | | | | | | | | | Remove dependency of SDWA pass on SIShrinkInstructions. The goal is to move SDWA even higher in the stack to avoid second run of MachineLICM, MachineCSE and SIFoldOperands. Also added handling to preserve original src modifiers. Differential Revision: https://reviews.llvm.org/D33860 llvm-svn: 304665
* [X86][SSE] Add SCALAR_TO_VECTOR(PEXTRW/PEXTRB) support to faux shuffle combiningSimon Pilgrim2017-06-031-9/+31
| | | | | | Generalized existing SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT) code to support AssertZext + PEXTRW/PEXTRB cases as well. llvm-svn: 304659
* [LazyValueInfo] Use Type::getIntegerBitWidth instead of casting to ↵Craig Topper2017-06-031-2/+1
| | | | | | IntegerType to call getBitWidth. NFC llvm-svn: 304656
* [LazyValueInfo] Make solveBlockValueCast take a CastInst* instead of ↵Craig Topper2017-06-031-18/+18
| | | | | | Instruction*. Makes getOpcode return the appropriate enum without a cast. NFC llvm-svn: 304655
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+1
| | | | llvm-svn: 304638
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-031-0/+1
| | | | llvm-svn: 304637
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-032-0/+3
| | | | llvm-svn: 304636
* Added LLVM_FALLTHROUGH to address warning: this statement may fall through. NFC.Galina Kistanova2017-06-032-0/+3
| | | | llvm-svn: 304635
* [WebAssembly] Refactor WasmObjectWriter::writeObjectSam Clegg2017-06-031-402/+483
| | | | | | | | | | The size of this function was getting a little out of. control. Split code for writing each section type into seperate functions. Differential Revision: https://reviews.llvm.org/D33792 llvm-svn: 304634
* [sanitizer-coverage] one more flavor of coverage: ↵Kostya Serebryany2017-06-031-9/+43
| | | | | | -fsanitize-coverage=inline-8bit-counters. Experimental so far, not documenting yet. llvm-svn: 304630
* AMDGPU/GlobalISel: Mark 1-bit integer constants as legalTom Stellard2017-06-031-0/+5
| | | | | | | | | | | | | | | | Summary: These are mostly legal, but will probably need special lowering for some cases. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D33791 llvm-svn: 304628
* [CodeGen] Fix Windows builds which treat warnings as errors, broken in r304621.Eugene Zelenko2017-06-031-1/+1
| | | | llvm-svn: 304627
* Revert "[CFI] Remove LinkerSubsectionsViaSymbols."Evgeniy Stepanov2017-06-031-12/+23
| | | | | | This reverts commit r304582: breaks cfi-devirt :: anon-namespace.cpp on Darwin. llvm-svn: 304626
* [AMDGPU] Preserve operand order in SIFoldOperandsStanislav Mekhanoshin2017-06-031-3/+18
| | | | | | | | | SIFoldOperands can commute operands even if no folding was done. This change is to preserve IR is no folding was done. Differential Revision: https://reviews.llvm.org/D33802 llvm-svn: 304625
* [PDB] Fix use after free.Zachary Turner2017-06-039-51/+59
| | | | | | | | | | | | | | | | | | | | | | | Previously MappedBlockStream owned its own BumpPtrAllocator that it would allocate from when a read crossed a block boundary. This way it could still return the user a contiguous buffer of the requested size. However, It's not uncommon to open a stream, read some stuff, close it, and then save the information for later. After all, since the entire file is mapped into memory, the data should always be available as long as the file is open. Of course, the exception to this is when the data isn't *in* the file, but rather in some buffer that we temporarily allocated to present this contiguous view. And this buffer would get destroyed as soon as the strema was closed. The fix here is to force the user to specify the allocator, this way it can provide an allocator that has whatever lifetime it chooses. Differential Revision: https://reviews.llvm.org/D33858 llvm-svn: 304623
* LiveRegUnits: Port recent LivePhysRegs bugfixesMatthias Braun2017-06-032-27/+32
| | | | | | | | Adjust code to look more like the code in LivePhysRegs and port over the fix for LivePhysRegs from r304001 and adapt to the new CSR management in MachineRegisterInfo. llvm-svn: 304622
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-031-59/+62
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 304621
* [AMDGPU] V_DIV_FIXUP_F16 is not a commutable operationStanislav Mekhanoshin2017-06-031-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D33808 llvm-svn: 304619
* [SLP] Improve comments and naming of functions/variables/members, NFC.Alexey Bataev2017-06-031-91/+59
| | | | | | | | | Fixed some comments, added an additional description of the algorithms, improved readability of the code. Differential revision: https://reviews.llvm.org/D33320 llvm-svn: 304616
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