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* NewGVN: Start making use of predicateinfo pass.Daniel Berlin2017-02-181-18/+275
| | | | | | | | | | | | Summary: This begins using the predicateinfo pass in NewGVN. Reviewers: davide Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D29682 llvm-svn: 295583
* NewGVN: Make ranking prefer undef to constants. Fix direction ofDaniel Berlin2017-02-181-8/+9
| | | | | | shouldSwapOperands to be correct. llvm-svn: 295582
* PredicateInfo: Clean up predicate info a little, using insertionDaniel Berlin2017-02-181-67/+93
| | | | | | helpers, and fixing support for the renaming the comparison. llvm-svn: 295581
* Fix signed/unsigned comparison warning.Simon Pilgrim2017-02-181-2/+2
| | | | llvm-svn: 295580
* [X86][XOP] Reduce the size of a multiclass by moving more stuff to ↵Craig Topper2017-02-184-70/+42
| | | | | | | | parameters instead of doing 128-bit and 256-bit simultaneously. This requires some instructions to be renamed to move the Y earlier in the instruction name. The new names are more consistent with other instructions. llvm-svn: 295579
* [AArch64] Fix enumeral/non-enumeral conditional expression warning.Simon Pilgrim2017-02-181-4/+4
| | | | | | gcc only allows you to mix enums / ints if they have the same signedness. llvm-svn: 295577
* [X86] Fix enumeral/non-enumeral comparison warning.Simon Pilgrim2017-02-181-1/+1
| | | | | | gcc only allows you to mix enums / ints if they have the same signedness. llvm-svn: 295576
* [X86][SSE] Avoid repeated calls to SDValue::getValueType.Simon Pilgrim2017-02-181-4/+7
| | | | | | Added assertion to check input type of X86ISD::VZEXT during target known bits calculation. llvm-svn: 295575
* [InstCombine] add nsw/nuw X, signbit --> or X, signbitSanjay Patel2017-02-181-2/+9
| | | | | | | | | Changing to 'or' (rather than 'xor' when no wrapping flags are set) allows icmp simplifies to happen as expected. Differential Revision: https://reviews.llvm.org/D29729 llvm-svn: 295574
* [InstSimplify] add nsw/nuw (xor X, signbit), signbit --> XSanjay Patel2017-02-181-1/+11
| | | | | | | | | The change to InstCombine in: https://reviews.llvm.org/D29729 ...exposes this missing fold in InstSimplify, so adding this first to avoid a regression. llvm-svn: 295573
* Recommit "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."Craig Topper2017-02-183-65/+22
| | | | | | Clang has now been fixed to not use these intrinsics. llvm-svn: 295571
* [x86] fold sext (xor Bool, -1) --> sub (zext Bool), 1Sanjay Patel2017-02-181-0/+10
| | | | | | | This is the same transform that is current used for: select Bool, 0, -1 llvm-svn: 295568
* [MemorySSA] NFC small fixesPiotr Padlewski2017-02-181-9/+6
| | | | | | | | | | | | | | Summary: 2 small fixes extracted from https://reviews.llvm.org/D29064 Reviewers: kuhar, davide, dberlin, george.burgess.iv Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30109 llvm-svn: 295566
* Revert "[X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR."Craig Topper2017-02-183-22/+65
| | | | | | This reverts r295564. I missed that clang was still using the intrinsics despite our half implemented autoupgrade support. llvm-svn: 295565
* [X86] Remove XOP VPCMOV intrinsics and autoupgrade them to native IR.Craig Topper2017-02-183-65/+22
| | | | | | It seems we were already upgrading 128-bit VPCMOV, but the intrinsic was still defined and being used in isel patterns. While I was here I also simplified the tablegen multiclasses. llvm-svn: 295564
* [X86][IR] Simplify the XOP vpcmov autoupgrade code. NFCCraig Topper2017-02-181-7/+3
| | | | llvm-svn: 295563
* [X86][IR] Merge together some very similar AutoUpgrade handling. NFCCraig Topper2017-02-181-24/+16
| | | | llvm-svn: 295562
* AMDGPU: Fix assembler subtarget predicate for gfx9Matt Arsenault2017-02-183-1/+13
| | | | | | This was accepting GFX9 instructions on VI. llvm-svn: 295557
* AMDGPU: Fix disassembly of aperture registersMatt Arsenault2017-02-181-0/+5
| | | | llvm-svn: 295555
* AMDGPU: Merge initial gfx9 supportMatt Arsenault2017-02-1818-41/+239
| | | | llvm-svn: 295554
* Refactor instruction simplification code in visitors. NFC.Easwaran Raman2017-02-181-88/+67
| | | | | | | | | | | | | | Several visitors check if operands to the instruction are constants, either as it is or after looking up SimplifiedValues, check if the result is a constant and update the SimplifiedValues map. This refactoring splits it into a common function that does the checking of whether the operands are constants and updating of the SimplifiedValues table, and an instruction specific part that is implemented by each instruction visitor as a lambda and passed to the common function. Differential revision: https://reviews.llvm.org/D30104 llvm-svn: 295552
* [AVX-512] Remove 128/256-bit masked fp max/min intrinsics. Upgrade them to ↵Craig Topper2017-02-182-8/+38
| | | | | | legacy unmasked intrinsics and select instructions. llvm-svn: 295543
* AMDGPU/R600: Assert on infinite loop in EmitClauseMarkersJan Vesely2017-02-181-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D29792 llvm-svn: 295539
* Increases full-unroll threshold.Dehao Chen2017-02-183-31/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The default threshold for fully unroll is too conservative. This patch doubles the full-unroll threshold This change will affect the following speccpu2006 benchmarks (performance numbers were collected from Intel Sandybridge): Performance: 403 0.11% 433 0.51% 445 0.48% 447 3.50% 453 1.49% 464 0.75% Code size: 403 0.56% 433 0.96% 445 2.16% 447 2.96% 453 0.94% 464 8.02% The compiler time overhead is similar with code size. Reviewers: davidxl, mkuper, mzolotukhin, hfinkel, chandlerc Reviewed By: hfinkel, chandlerc Subscribers: mehdi_amini, zzheng, efriedma, haicheng, hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D28368 llvm-svn: 295538
* [IR/Verifier] Don't visit DISubprograms more than needed.Davide Italiano2017-02-181-2/+0
| | | | | | | | | | | | | Before this patch we happened to visit twice, one when scanning MDNodes and the other one while visiting the function. Remove the explicit call to visitDISubprogram there, so we don't emit the same error twice in case the verifier fail and we save some time when running it. Thanks to Justin Bogner for the report and Adrian for the quick review! PR: 31995 llvm-svn: 295537
* [AVR] Set UseIntegratedAssemblerDylan McKay2017-02-181-0/+1
| | | | llvm-svn: 295535
* OptDiag: Allow constructing DiagnosticLocation from DISubprogramsJustin Bogner2017-02-182-3/+10
| | | | | | | | This avoids creating a DILocation just to represent a line number, since creating Metadata is expensive. Creating a DiagnosticLocation directly is much cheaper. llvm-svn: 295531
* Don't assume little endian in StreamReader / StreamWriter.Zachary Turner2017-02-1815-152/+75
| | | | | | | In an effort to generalize this so it can be used by more than just PDB code, we shouldn't assume little endian. llvm-svn: 295525
* OptDiag: Decouple backend diagnostics from debug info metadataJustin Bogner2017-02-182-52/+49
| | | | | | | | | This creates and uses a DiagnosticLocation type rather than using DebugLoc for this purpose in the backend diagnostics. This is NFC for now, but will allow us to create locations for diagnostics without having to create new metadata nodes when we don't have a DILocation. llvm-svn: 295519
* MachineRegionInfo: Fix pass initializationMatthias Braun2017-02-183-9/+14
| | | | | | | | | | | | | | | | - Adapt MachineBasicBlock::getName() to have the same behavior as the IR BasicBlock (Value::getName()). - Add it to lib/CodeGen/CodeGen.cpp::initializeCodeGen so that it is linked in the CodeGen library. - MachineRegionInfoPass's name conflicts with RegionInfoPass's name ("region"). - MachineRegionInfo should depend on MachineDominatorTree, MachinePostDominatorTree and MachineDominanceFrontier instead of their respective IR versions. - Since there were no tests for this, add a X86 MIR test. Patch by Francis Visoiu Mistrih<fvisoiumistrih@apple.com> llvm-svn: 295518
* Verifier: Disallow a line number without a file in DISubprogramJustin Bogner2017-02-171-0/+2
| | | | | | | | A line number doesn't make much sense if you don't say where it's from. Add a verifier check for this and update some tests that had bogus debug info. llvm-svn: 295516
* AArch64LoadStoreOptimizer: Correctly clear kill flagsMatthias Braun2017-02-171-2/+4
| | | | | | | | | | | When promoting the Load of a Store-Load pair to a COPY all kill flags between the store and the load need to be cleared. rdar://30402435 Differential Revision: https://reviews.llvm.org/D30110 llvm-svn: 295512
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-02-171-0/+4
| | | | | | | | | | | | Newer ppc supports unaligned memory access, it reduces the cost of unaligned memory access significantly. This patch handles this case in PPCTTIImpl::getMemoryOpCost. This patch fixes pr31492. Differential Revision: https://reviews.llvm.org/D28630 This is resubmit of r292680, which was reverted by r293092. The internal application failures were actually caused by a source code bug. llvm-svn: 295506
* [CodeGen] Revert changes in LowLevelType to pre-r295499 to fix broken buildbots.Eugene Zelenko2017-02-171-7/+1
| | | | llvm-svn: 295505
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1718-116/+271
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* [NewGVN] isOnlyReachableViaThisEdge() is dead now. NFCI.Davide Italiano2017-02-171-18/+0
| | | | llvm-svn: 295503
* [X86] Simplify by pulling out valuetype. NFCI.Simon Pilgrim2017-02-171-2/+2
| | | | llvm-svn: 295502
* [NewGVN] createVariableOrConstant is not required anymore. NFCI.Davide Italiano2017-02-171-8/+0
| | | | llvm-svn: 295500
* [CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-02-176-26/+63
| | | | | | other minor fixes (NFC). llvm-svn: 295499
* [LAA] Remove unused code (NFC)Matthew Simpson2017-02-171-5/+0
| | | | llvm-svn: 295493
* [X86][SSE] Add (V)MOVD folding pattern with zextloadi64i32 load node.Simon Pilgrim2017-02-172-0/+6
| | | | | | Fixes PRPR31309 llvm-svn: 295492
* AMDGPU: Fix crashes on invalid icmp/fcmp intrinsicsMatt Arsenault2017-02-171-5/+9
| | | | llvm-svn: 295489
* WholeProgramDevirt: For VCP use a 32-bit ConstantInt for the byte offset.Peter Collingbourne2017-02-171-1/+1
| | | | | | | | | | | | | | | A future change will cause this byte offset to be inttoptr'd and then exported via an absolute symbol. On the importing end we will expect the symbol to be in range [0,2^32) so that it will fit into a 32-bit relocation. The problem is that on 64-bit architectures if the offset is negative it will not be in the correct range once we inttoptr it. This change causes us to use a 32-bit integer so that it can be inttoptr'd (which zero extends) into the correct range. Differential Revision: https://reviews.llvm.org/D30016 llvm-svn: 295487
* Debug Info: Sort frame index expressions before emitting them.Adrian Prantl2017-02-173-36/+44
| | | | | | | | | | This fixes PR31381, which caused an assertion and/or invalid debug info. This affects debug variables that have multiple fragments in the MMI side (i.e.: in the stack frame) table. rdar://problem/30571676 llvm-svn: 295486
* In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3Artyom Skrobov2017-02-171-17/+14
| | | | | | | | | | | | Reviewers: jmolloy, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, llvm-commits Differential Revision: https://reviews.llvm.org/D30097 llvm-svn: 295478
* GlobalISel: verify that generic loads & stores have a mem operand.Tim Northover2017-02-171-0/+8
| | | | | | | The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
* [AArch64] Add Cavium ThunderX supportJoel Jones2017-02-175-2/+415
| | | | | | | | | | | | | | This set of patches adds support for Cavium ThunderX ARM64 processors: * ThunderX * ThunderX T81 * ThunderX T83 * ThunderX T88 Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D28891 llvm-svn: 295475
* WholeProgramDevirt: Examine the function body when deciding whether ↵Peter Collingbourne2017-02-171-12/+41
| | | | | | | | | | functions are readnone. The goal is to get an analysis result even for de-refineable functions. Differential Revision: https://reviews.llvm.org/D29803 llvm-svn: 295472
* OptDiag: Rename DiagnosticInfoWithDebugLoc to WithLocation. NFCJustin Bogner2017-02-171-3/+3
| | | | | | | This generalizes the name in preparation for decoupling the concept from DebugLoc. llvm-svn: 295465
* MC/COFF: Do not emit forward associative section referenceds.Rui Ueyama2017-02-171-26/+53
| | | | | | | | | | | | | | | | MSVC link.exe cannot handle associative sections that refer later sections in the section header. Technically, such COFF object doesn't violate the Microsoft COFF spec, as the spec doesn't say anything about that, but still we should avoid doing that to make it compatible with MS tools. This patch assigns smaller section numbers to non-associative sections and larger numbers to associative sections. This should resolve the compatibility issue. Differential Revision: https://reviews.llvm.org/D30080 llvm-svn: 295464
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