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* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-1321-447/+104
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* Remove unused and odd code.Rafael Espindola2014-06-132-15/+0
| | | | | | | | This code was never being used and any use of it would look fairly strange. For example, it would try to map a object_error::parse_failed to std::errc::invalid_argument. llvm-svn: 210912
* SCCP: update for cmpxchg returning { iN, i1 } now.Tim Northover2014-06-131-1/+3
| | | | | | I accidentally missed this one since its use looked OK locally. llvm-svn: 210909
* [mips][mips64r6] Relocation R_MIPS_PC18_S3Zoran Jovanovic2014-06-135-5/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D3890 llvm-svn: 210908
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-1321-117/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
* [mips] Add cache and pref instructionsDaniel Sanders2014-06-136-13/+101
| | | | | | | | | | | | | | | | | | | Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
* [mips][mips64r6] bc1any[24] are not available on MIPS32r6/MIPS64r6Daniel Sanders2014-06-131-1/+0
| | | | | | | | | | | | | | Summary: These MIPS-3D instructions have never been implemented in LLVM so we only add testcases. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4115 llvm-svn: 210899
* [mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal ↵Daniel Sanders2014-06-135-13/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
* [mips][mips64r6] daddi is not available on MIPS64r6Daniel Sanders2014-06-132-5/+16
| | | | | | | | | | | | | | | | | | Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
* Add HasCDI predicate to AVX512 VPBROADCASTM*.Cameron McInally2014-06-131-0/+2
| | | | llvm-svn: 210892
* CPP backend: set volatile property on atomic instructions.Tim Northover2014-06-131-0/+4
| | | | llvm-svn: 210890
* ARM: Fix fastcc calling convention for Thumb1Oliver Stannard2014-06-131-3/+3
| | | | | | | | When targetting Thumb1 on a processor which has a VFP unit (which is not accessible from Thumb1), we were converting the fastcc calling convention to AAPCS-VFP, which is not possible. llvm-svn: 210889
* R600: Don't call setOperationAction with things that aren't opcodes.Matt Arsenault2014-06-131-8/+0
| | | | | | | | | CondCode actions are set with setCondCodeAction. This should have been a harmless bug since the values seem to only collide only with nodes that don't need to be handled, and these are already correctly setup elsewhere. llvm-svn: 210888
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-132-6/+7
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* Fix build on windows.Rafael Espindola2014-06-132-85/+90
| | | | llvm-svn: 210873
* Remove 'using std::errro_code' from lib.Rafael Espindola2014-06-1342-580/+562
| | | | llvm-svn: 210871
* [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.Juergen Ributzka2014-06-131-0/+66
| | | | | | | | This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding insertelement instructions are folded into the conversion instruction (if possible). llvm-svn: 210870
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-1323-43/+54
| | | | llvm-svn: 210869
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-131-1/+2
| | | | llvm-svn: 210868
* Remove all uses of 'using std::error_code' from headers.Rafael Espindola2014-06-135-32/+33
| | | | llvm-svn: 210866
* R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cppTom Stellard2014-06-131-1/+1
| | | | llvm-svn: 210865
* [FastISel][X86] - Add branch weightsJuergen Ributzka2014-06-132-5/+22
| | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). llvm-svn: 210863
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-134-7/+7
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-134-76/+87
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* [DWARF parser] Fix broken address ranges construction.Alexey Samsonov2014-06-122-60/+56
| | | | | | | | | | | | | | | | | Previous algorithm for constructing [Address ranges]->[Compile Units] mapping was wrong. It somewhat relied on the assumption that address ranges for different compile units may not overlap. It is not so. For example, two compile units may contain the definition of the same linkonce_odr function. These definitions will be merged at link-time, resulting in equivalent .debug_ranges entries for both these units Instead of sorting and merging original address ranges (from .debug_ranges and .debug_aranges), implement a different approach: save endpoints of all ranges, and then use a sweep-line approach to construct the desired mapping. If we find that certain address maps to several compilation units, we just pick any of them. llvm-svn: 210860
* Have ARMSelectionDAGInfo take a DataLayout as it's argument as theEric Christopher2014-06-123-14/+11
| | | | | | | DAG has access to the subtarget and TargetSelectionDAGInfo only needs a DataLayout. llvm-svn: 210859
* [FastISel][X86] Add MachineMemOperand to load/store instructions.Juergen Ributzka2014-06-122-39/+112
| | | | | | | | This commit adds MachineMemOperands to load and store instructions. This allows the peephole optimizer to fold load instructions. Unfortunatelly the peephole optimizer currently doesn't run at -O0. llvm-svn: 210858
* Move the PPCSelectionDAGInfo off the TargetMachine and onto theEric Christopher2014-06-124-5/+6
| | | | | | subtarget. llvm-svn: 210854
* Make PPCSelectionDAGInfo take a DataLayout instead of a TargetMachineEric Christopher2014-06-123-7/+6
| | | | | | since that's all it needs. llvm-svn: 210853
* Move PPCTargetLowering off of the TargetMachine and onto the subtarget.Eric Christopher2014-06-125-8/+11
| | | | llvm-svn: 210852
* Remove an extraneous this-> to access the subtarget.Eric Christopher2014-06-121-1/+1
| | | | llvm-svn: 210849
* Rename PPCSubTarget to Subtarget in PPCTargetLowering for consistency.Eric Christopher2014-06-122-126/+124
| | | | | | Also remove an extra local subtarget in the initialization functions. llvm-svn: 210848
* Fix the scheduler's MaxObservedStall computation.Andrew Trick2014-06-121-2/+6
| | | | | | | WenHan Gu pointed out this bug that results in an assert not being effective in some cases. llvm-svn: 210846
* Move PPCJITInfo off of the TargetMachine and onto the subtarget.Eric Christopher2014-06-126-30/+33
| | | | | | | Needed to migrate a few functions around to avoid circular header dependencies. llvm-svn: 210845
* Remove the use of TargetMachine from PPCJITInfo and replace withEric Christopher2014-06-123-6/+6
| | | | | | | the subtarget. Also remove unnecessary argument to the constructor at the same time, we already have access via the subtarget. llvm-svn: 210844
* Move PPCInstrInfo off of the target machine and onto the subtarget.Eric Christopher2014-06-124-7/+11
| | | | llvm-svn: 210839
* Try to fix the windows build.Rafael Espindola2014-06-121-1/+1
| | | | llvm-svn: 210837
* Remove TargetMachine from PPCInstrInfo and all dependencies andEric Christopher2014-06-125-27/+29
| | | | | | replace with the current subtarget. llvm-svn: 210836
* Don't use 'using std::error_code' in include/llvm.Rafael Espindola2014-06-1245-78/+121
| | | | | | This should make sure that most new uses use the std prefix. llvm-svn: 210835
* GVN: Enable value forwarding for callocDuncan P. N. Exon Smith2014-06-121-0/+16
| | | | | | | | | | | | | | | | | | | | | Enable value forwarding for loads from `calloc()` without an intervening store. This change extends GVN to handle the following case: %1 = tail call noalias i8* @calloc(i64 1, i64 4) %2 = bitcast i8* %1 to i32* ; This load is trivially constant zero %3 = load i32* %2, align 4 This is analogous to the handling for `malloc()` in the same places. `malloc()` returns `undef`; `calloc()` returns a zero value. Note that it is correct to return zero even for out of bounds GEPs since the result of such a GEP would be undefined. Patch by Philip Reames! llvm-svn: 210828
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-128-240/+32
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* Move DataLayout from the PPCTargetMachine to the subtarget.Eric Christopher2014-06-124-40/+46
| | | | llvm-svn: 210824
* Move PPCFrameLowering into PPCSubtarget from PPCTargetMachine. UseEric Christopher2014-06-126-196/+211
| | | | | | | | the initializeSubtargetDependencies code to obtain an initialized subtarget and migrate a couple of subtarget using functions to the .cpp file to avoid circular includes. llvm-svn: 210822
* [FastIsel][X86] Add support for lowering the first 8 floating-point arguments.Juergen Ributzka2014-06-121-20/+41
| | | | | | | Recommit with fixed argument attribute checking code, which is required to bail out of all the cases we don't handle yet. llvm-svn: 210815
* CodeGen: enable mov.w/mov.t pairs with minsize for WoASaleem Abdulrasool2014-06-121-1/+6
| | | | | | | | | Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. llvm-svn: 210814
* Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point ↵Juergen Ributzka2014-06-121-36/+19
| | | | | | | | arguments." Reverting it because it breaks several tests. llvm-svn: 210810
* [llvm-symbolizer] Fix parsing DW_AT_ranges in Fission skeleton compile unit ↵Alexey Samsonov2014-06-121-3/+9
| | | | | | | | | | | | | DIEs. Turns out that DW_AT_ranges_base attribute sets the offset for DW_AT_ranges values specified in the .dwo file, but not for DW_AT_ranges specified in the skeleton compile unit DIE in the main executable. This is extremely confusing, and would hopefully be fixed in DWARF-5 when it's finalized. For now this behavior makes sense, as otherwise Fission would break DWARF consumers who doesn't know anything about DW_AT_ranges_base. llvm-svn: 210809
* Revert r210721 as it causes breakage in internal builds (and possibly GDB).Eli Bendersky2014-06-121-109/+6
| | | | llvm-svn: 210807
* X86: stifle GCC warningSaleem Abdulrasool2014-06-121-1/+3
| | | | | | | | | | lib/Target/X86/X86TargetTransformInfo.cpp: In member function ‘virtual unsigned int {anonymous}::X86TTI::getIntImmCost(unsigned int, unsigned int, const llvm::APInt&, llvm::Type*) const’: lib/Target/X86/X86TargetTransformInfo.cpp:920:60: warning: enumeral and non-enumeral type in conditional expression [enabled by default] This seems like an unhelpful warning, but there doesnt seem to be a controlling flag, so add an explicit cast to silence the warning. llvm-svn: 210806
* Trying to fix the windows build.Rafael Espindola2014-06-121-4/+3
| | | | llvm-svn: 210805
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