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* [lanai] Add computeKnownBitsForTargetNode for Lanai.Jacques Pienaar2017-05-093-5/+29
| | | | | | | | | | | | | | Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions. Reviewers: eliben, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29605 llvm-svn: 302568
* [NewGVN] Explain why sorting by pointer values doesn't introduce ↵Davide Italiano2017-05-091-0/+4
| | | | | | | | non-determinism. Thanks to Eli for pointing out in a post-commit review comment. llvm-svn: 302566
* [SystemZ] Support missing relocation types in RuntimeDyldELFUlrich Weigand2017-05-091-3/+18
| | | | | | | | | Handle some more relocation types in RuntimeDyldELF::resolveSystemZRelocation This fixes a number of failing LLDB test cases. llvm-svn: 302565
* [WebAssembly] Fix validation of start functionSam Clegg2017-05-091-1/+1
| | | | | | | | | | The check for valid start function was inverted. Added a new test in test/Object to check this case and fixed the existing tests in for ObjectYAML. Differential Revision: https://reviews.llvm.org/D32986 llvm-svn: 302560
* [RegScavenger] Rangify a loop, NFCKrzysztof Parzyszek2017-05-091-4/+3
| | | | llvm-svn: 302554
* [NewGVN] Fix a consistent order for phi nodes operands.Davide Italiano2017-05-091-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | | The way we currently define congruency for two PHIExpression(s) is: 1) The operands to the phi functions are congruent 2) The PHIs are defined in the same BasicBlock. NewGVN works under the assumption that phi operands are in predecessor order, or at least in some consistent order. OTOH, is valid IR: patatino: %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ] %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ] br label %end and the in-memory representations of the two SSA registers have an inconsistent order. This violation of NewGVN assumptions results into two PHIs found congruent when they're not. While we think it's useful to have always a consistent order enforced, let's fix this in NewGVN sorting uses in predecessor order before creating a PHI expression. Differential Revision: https://reviews.llvm.org/D32990 llvm-svn: 302552
* [APInt] Remove return value from tcFullMultiply.Craig Topper2017-05-091-11/+5
| | | | | | | | The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you. No one uses the result today so rather than try to fix it, just remove it. llvm-svn: 302551
* NewGVN: Make all of symbolic evaluation logically const.Daniel Berlin2017-05-091-64/+74
| | | | llvm-svn: 302550
* [X86] Add more patterns for BZHI iselCraig Topper2017-05-091-0/+32
| | | | | | | | | | | | | | | | | | | | | | This patch adds more patterns that a reasonable person might write that can be compiled to BZHI. This adds support for (~0U >> (32 - b)) & a; and a << (32 - b) >> (32 - b); This was inspired by the code in APInt::clearUnusedBits. This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case. I think this is still missing cases where the subtract portion is an 8-bit operation. Differential Revision: https://reviews.llvm.org/D32616 llvm-svn: 302549
* [InstCombineCasts] Fix checks in sext->lshr->trunc pattern.Sanjay Patel2017-05-091-6/+14
| | | | | | | | | | | | | | | The comment says to avoid the case where zero bits are shifted into the truncated value, but the code checks that the shift is smaller than the truncated value instead of the number of bits added by the sign extension. Fixing this allows a shift by more than the value size to be introduced, which is undefined behavior, so the shift is capped at the value size minus one, which has the expected behavior of filling the value with the sign bit. Patch by Jacob Young! Differential Revision: https://reviews.llvm.org/D32285 llvm-svn: 302548
* VX512] Only look at lower bit in constant scalar masksGuy Blank2017-05-091-2/+4
| | | | | | | | | for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit. This patch handles cases where the lower bit is '1'. Differential Revision: https://reviews.llvm.org/D32805 llvm-svn: 302546
* Re-land "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-094-41/+68
| | | | | | This re-lands r302483. It was not the cause of PR32977. llvm-svn: 302544
* Re-land "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-091-14/+0
| | | | | | This re-lands commit r302461. It was not the cause of PR32977. llvm-svn: 302543
* [Atomic] Remove IsStore/IsLoad in the interface, and pass the instruction ↵Tim Shen2017-05-096-44/+55
| | | | | | | | | | | | | | | | | instead. NFC. Now both emitLeadingFence and emitTrailingFence take the instruction itself, instead of taking IsLoad/IsStore pairs. Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used for determining those two booleans. The instruction argument is also useful for later D32763, in emitTrailingFence. For emitLeadingFence, it seems to have cleaner interface with the proposed change. Differential Revision: https://reviews.llvm.org/D32762 llvm-svn: 302539
* Amend r302535; ifndef and ifdef are different, as it turns out.Aaron Ballman2017-05-091-1/+1
| | | | llvm-svn: 302537
* ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it ↵Aaron Ballman2017-05-091-0/+2
| | | | | | is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail. llvm-svn: 302535
* Revert r302469 "Make it illegal for two Functions to point to the same ↵Hans Wennborg2017-05-094-156/+46
| | | | | | | | | | | | | | | | | | | | | | | | DISubprogram" This caused PR32977. Original commit message: > Make it illegal for two Functions to point to the same DISubprogram > > As recently discussed on llvm-dev [1], this patch makes it illegal for > two Functions to point to the same DISubprogram and updates > FunctionCloner to also clone the debug info of a function to conform > to the new requirement. To simplify the implementation it also factors > out the creation of inlineAt locations from the Inliner into a > general-purpose utility in DILocation. > > [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html > <rdar://problem/31926379> > > Differential Revision: https://reviews.llvm.org/D32975 llvm-svn: 302533
* [LV] Fix insertion point for shuffle vectors in first order recurrenceAnna Thomas2017-05-091-2/+5
| | | | | | | | | | | | | | | | | | Summary: In first order recurrence vectorization, when the previous value is a phi node, we need to set the insertion point to the first non-phi node. We can have the previous value being a phi node, due to the generation of new IVs as part of trunc optimization [1]. [1] https://reviews.llvm.org/rL294967 Reviewers: mssimpso, mkuper Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32969 llvm-svn: 302532
* Removing a file that is not necessary (and was causing link diagnostics with ↵Aaron Ballman2017-05-092-11/+0
| | | | | | MSVC 2015); NFC. llvm-svn: 302531
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-0951-140/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* Revert "[MIPS] Add support to match more patterns for DINS instruction"Simon Dardis2017-05-091-59/+25
| | | | | | This reverts commit rL302512. This broke the mips buildbots. llvm-svn: 302526
* [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)Simon Pilgrim2017-05-091-0/+8
| | | | | | | | | | Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 llvm-svn: 302525
* Revert "[Dwarf] Disable reference verification for now (PR32972)"Diana Picus2017-05-091-2/+1
| | | | | | This reverts commit r302520 because it break the unit tests. llvm-svn: 302524
* [Dwarf] Disable reference verification for now (PR32972)Renato Golin2017-05-091-1/+2
| | | | | | | | | | | | | | | There is no other explanation about why this only started happening now, even though it crashes on old code (supposedly reachable from here). The only common factor between the failing bots is that they use GCC (4.9 and 5.3) to compile Clang, while the others use Clang 3.8, but the failure is while building the tests, as an assertion, on Clang. Commenting it out for now in hope the bots will go back green, but we should keep looking for the real cause, and update bugzilla. llvm-svn: 302520
* Introduce experimental generic intrinsics for horizontal vector reductions.Amara Emerson2017-05-0912-66/+480
| | | | | | | | | | | | | | - This change allows targets to opt-in to using them instead of the log2 shufflevector algorithm. - The SLP and Loop vectorizers have the common code to do shuffle reductions factored out into LoopUtils, and now have a unified interface for generating reductions regardless of the preference of the target. LoopUtils now uses TTI to determine what kind of reductions the target wants to handle. - For CodeGen, basic legalization support is added. Differential Revision: https://reviews.llvm.org/D30086 llvm-svn: 302514
* [X86] Clang option -fuse-init-array has no effect when generating for MCU targetNikolai Bozhenov2017-05-091-1/+1
| | | | | | | | | | | | | Reviewers: Eugene.Zelenko, dschuff, craig.topper Reviewed By: craig.topper Subscribers: ahatanak, aaboud, DavidKreitzer, llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D32543 Patch by AndreiGrischenko <andrei.l.grischenko@intel.com> llvm-svn: 302513
* [MIPS] Add support to match more patterns for DINS instructionStrahinja Petrovic2017-05-091-25/+59
| | | | | | | | | This patch adds support for recognizing patterns to match DINS instruction. Differential Revision: https://reviews.llvm.org/D31465 llvm-svn: 302512
* [ARM GlobalISel] Remove hand-written G_FADD selectionDiana Picus2017-05-091-26/+0
| | | | | | | Remove the code selecting G_FADD - now that TableGen can handle more opcodes, it's not needed anymore. llvm-svn: 302511
* [ConstantRange] Rewrite shl to avoid repeated calls to getUnsignedMax and ↵Craig Topper2017-05-091-7/+11
| | | | | | avoid creating the min APInt until we're sure we need it. Use inplace shift operations. llvm-svn: 302510
* [ConstantRange] Combine the two adds max+1 in lshr into a single addition.Craig Topper2017-05-091-4/+4
| | | | llvm-svn: 302509
* [ConstantRange] Use APInt::isNullValue in place of comparing with 0. The ↵Craig Topper2017-05-091-4/+4
| | | | | | compiler should be able to generate slightly better code for the former. NFC llvm-svn: 302508
* Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-091-0/+14
| | | | | | | | | | This reverts commit r302461. It appears to be causing failures compiling gtest with debug info on the Linux sanitizer bot. I was unable to reproduce the failure locally, however. llvm-svn: 302504
* Fix code section prefix for proper layoutTeresa Johnson2017-05-091-1/+1
| | | | | | | | | | | | | | | | | | Summary: r284533 added hot and cold section prefixes based on profile information, to enable grouping of hot/cold functions at link time. However, it used "cold" as the prefix for cold sections, but gold only recognizes "unlikely" (which is used by gcc for cold sections). Therefore, cold sections were not properly being grouped. Switch to using "unlikely" Reviewers: danielcdh, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32983 llvm-svn: 302502
* [libFuzzer] update docs on -print_coverage/-dump_coverageKostya Serebryany2017-05-091-4/+4
| | | | llvm-svn: 302498
* [libFuzzer] make sure the input data is not overwritten in the fuzz target ↵Kostya Serebryany2017-05-096-1/+39
| | | | | | (if it is -- report an error) llvm-svn: 302494
* Revert "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-094-68/+41
| | | | | | This reverts r302483 and it's follow up fix. llvm-svn: 302493
* [APInt] Use default constructor instead of explicitly creating a 1-bit APInt ↵Craig Topper2017-05-081-2/+2
| | | | | | | | in udiv and urem. NFC The default constructor does the same thing. llvm-svn: 302487
* [APInt] Remove 'else' after 'return' in udiv and urem. NFCCraig Topper2017-05-081-9/+7
| | | | llvm-svn: 302486
* Ignore !associated metadata with null argument.Evgeniy Stepanov2017-05-081-1/+5
| | | | | | | Fixes PR32577 (comment 10). Such metadata may legitimately appear in LTO. llvm-svn: 302485
* Use the frame index side table for byval and inalloca argumentsReid Kleckner2017-05-084-41/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For inalloca functions, this is a very common code pattern: %argpack = type <{ i32, i32, i32 }> define void @f(%argpack* inalloca %args) { entry: %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0 %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1 %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2 tail call void @llvm.dbg.declare(metadata i32* %a, ... "a") tail call void @llvm.dbg.declare(metadata i32* %c, ... "b") tail call void @llvm.dbg.declare(metadata i32* %b, ... "c") Even though these GEPs can be simplified to a constant offset from EBP or RSP, we don't do that at -O0, and each GEP is computed into a register. Registers used to compute argument addresses are typically spilled and clobbered very quickly after the initial computation, so live debug variable tracking loses information very quickly if we use DBG_VALUE instructions. This change moves processing of dbg.declare between argument lowering and basic block isel, so that we can ask if an argument has a frame index or not. If the argument lives in a register as is the case for byval arguments on some targets, then we don't put it in the side table and during ISel we emit DBG_VALUE instructions. Reviewers: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32980 llvm-svn: 302483
* [InstNamer] Use range-forSanjoy Das2017-05-081-4/+3
| | | | llvm-svn: 302481
* [InstNamer] Don't check type of arguments (they're never void)Sanjoy Das2017-05-081-1/+1
| | | | llvm-svn: 302480
* Delete trailing whitespaceSanjoy Das2017-05-081-3/+3
| | | | llvm-svn: 302479
* Add const to "DWARFDie &Die" in a few functions as they can't change the ↵Greg Clayton2017-05-081-2/+2
| | | | | | DWARFDie. llvm-svn: 302471
* Fix typoEugene Zemtsov2017-05-081-1/+1
| | | | llvm-svn: 302470
* Make it illegal for two Functions to point to the same DISubprogramAdrian Prantl2017-05-084-46/+156
| | | | | | | | | | | | | | | | As recently discussed on llvm-dev [1], this patch makes it illegal for two Functions to point to the same DISubprogram and updates FunctionCloner to also clone the debug info of a function to conform to the new requirement. To simplify the implementation it also factors out the creation of inlineAt locations from the Inliner into a general-purpose utility in DILocation. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html <rdar://problem/31926379> Differential Revision: https://reviews.llvm.org/D32975 llvm-svn: 302469
* Fix typo "veify" to "verify".Greg Clayton2017-05-081-1/+1
| | | | llvm-svn: 302466
* [InstCombine] add folds for not-of-shift-rightSanjay Patel2017-05-081-15/+32
| | | | | | | | | | | | | | | This is another step towards getting rid of dyn_castNotVal, so we can recommit: https://reviews.llvm.org/rL300977 As the tests show, we were missing the lshr case for constants and both ashr/lshr vector splat folds. The ashr case with constant was being performed inefficiently in 2 steps. It's also possible there was a latent bug in that case because we can't do that fold if the constant is positive: http://rise4fun.com/Alive/Bge llvm-svn: 302465
* [PartialInlining] Capture by reference rather than by value.Davide Italiano2017-05-081-3/+3
| | | | llvm-svn: 302464
* ARM: use divmod libcalls on embedded MachO platforms too.Tim Northover2017-05-081-3/+3
| | | | | | | The separated libcalls are implemented in terms of __divmodsi4 and __udivmodsi4 anyway, so we should always use them if possible. llvm-svn: 302462
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